Electronis Discussion
0 votes

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0.


If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is ____________

in Digital Circuits by (2.7k points)
edited by

Please log in or register to answer this question.

Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.
1,044 questions
44 answers
42,757 users