A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin $NM_{L}$ and the HIGH noise margin $NM_{H}$?
1. $NM_{L}$ increases and $NM_{H}$ decreases.
2. $NM_{L}$ decreases and $NM_{H}$ increases.
3. Both $NM_{L}$ and $NM_{H}$ increases.