Electronis Discussion
0 votes


  1. GATE2019-65
  2. GATE2019-65
  3. GATE2019-65
  4. GATE2019-65

A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased what would be the effect on the LOW noise margin $NM_{L}$ and the HIGH noise margin $NM_{H}$?

  1. $NM_{L}$ increases and $NM_{H}$ decreases.
  2. $NM_{L}$ decreases and $NM_{H}$ increases.
  3. Both $NM_{L}$ and $NH_{H}$ increases.
  4. No change in the noise margins.
in Others by (1.4k points)
edited by

Please log in or register to answer this question.

Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.
1,042 questions
39 answers
42,712 users