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For the circuit shown, the clock frequency is $f_{0}$ and the duty cycle is $25 \%.$ For the signal at the $\text{Q}$ output of the Flip-Flop, _______________.

  1. frequency is $f_{0}/4$ and duty cycle is $50 \%$
  2. frequency is $f_{0}/4$ and duty cycle is $25 \%$
  3. frequency is $f_{0}/2$ and duty cycle is $50 \%$
  4. frequency is $f_{0}$ and duty cycle is $25 \%$
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