For the circuit shown, the clock frequency is $f_{0}$ and the duty cycle is $25 \%.$ For the signal at the $\text{Q}$ output of the Flip-Flop, _______________.
- frequency is $f_{0}/4$ and duty cycle is $50 \%$
- frequency is $f_{0}/4$ and duty cycle is $25 \%$
- frequency is $f_{0}/2$ and duty cycle is $50 \%$
- frequency is $f_{0}$ and duty cycle is $25 \%$