For the circuit shown in the figure, $\mathrm{D}$ has a transition from $0$ to $1$ after $\text{CLK}$ changes from $1$ to $0 .$ Assume gate delays to be negligible.
Which of the following statements is true?
- $\text{Q}$ goes to $1$ at the $\text{CLK}$ transition and stays at $1.$
- $\text{Q}$ goes to $0$ at the $\text{CLK}$ transition and stays at $0.$
- $\text{Q}$ goes to $1$ at the $\text{CLK}$ transition and goes to $0$ when $\text{D}$ goes to $1.$
- $\text{Q}$ goes to $0$ at the $\text{CLK}$ transition and goes to $1$ when $\mathrm{D}$ goes to $1.$