in Others ago edited ago by
2 views
0 votes
0 votes

GATE ECE 2007 | Question-46

An $8255$ chip is interfaced to an $8085$ microprocessor system as an $\mathrm{I} / \mathrm{O}$ mapped $\mathrm{I} / \mathrm{O}$ as shown in the figure. The address lines $\mathrm{A}_{0}$ and $\mathrm{A}_{1}$ of the $8085$ are used by the $8255$ chip to decode internally its three ports and the Control register. The address lines $A_{3}$ to $\mathrm{A}_{7}$ as well as the $I O / \overline{M}$ signal are used for address decoding. The range of addresses for which the $8255$ chip would get selected is

  1. $\mathrm{F} 8 \mathrm{H}-\mathrm{FBH}$
  2. $\mathrm{F} 8 \mathrm{H}-\mathrm{FCH}$
  3. $\mathrm{F} 8 \mathrm{H}-\mathrm{FFH}$
  4. $\mathrm{F0H}-\mathrm{F} 7 \mathrm{H}$
in Others ago edited ago by
by
21.7k points
2 views

Please log in or register to answer this question.

Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.