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GATE ECE 2006 | Question-45

 

For the circuit shown in figure below, two $4$-bit parallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the outputs of the fulladder should be

  1. $\mathrm{S}=0, \mathrm{C}_{0}=0$
  2. $\mathrm{S}=0, \mathrm{C}_{0}=1$
  3. $\mathrm{S}=1, \mathrm{C}_{0}=0$
  4. $\mathrm{S}=1, \mathrm{C}_{0}=1$
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