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In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are,

- $X=’1’$, $Y=’1’$
- either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$
- either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$
- $X=’0’$, $Y=’0’$