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The circuit shown in the figure is a $4$ bit $\text{DAC}$


The input bits $0$ and $1$ are represented by $0$ and $5 \mathrm{~V}$ respectively. The $\text{OP AMP}$ is ideal, but all the resistances and the $5 \mathrm{~V}$ inputs have a tolerance of $\pm 10 \%$. The specification (rounded to the nearest multiple of $5 \%$ ) for the tolerance of the $\text{DAC}$ is

  1. $\pm 35 \%$
  2. $\pm 20 \%$
  3. $\pm 10 \%$
  4. $\pm 5 \%$
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