For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is
- $\overline{\mathrm{ABCDE}}$
- $(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\mathrm{D}+\mathrm{E}})$
- $\overline{\mathrm{A} \cdot(\mathrm{B}+\mathrm{C})+\mathrm{D} \cdot \mathrm{E}}$
- $(\overline{\mathrm{A}+\mathrm{B}}) \cdot \mathrm{C}+\overline{\mathrm{D}} \cdot \overline{\mathrm{E}}$