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For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is

  1. $\overline{\mathrm{ABCDE}}$
  2. $(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\mathrm{D}+\mathrm{E}})$
  3. $\overline{\mathrm{A} \cdot(\mathrm{B}+\mathrm{C})+\mathrm{D} \cdot \mathrm{E}}$
  4. $(\overline{\mathrm{A}+\mathrm{B}}) \cdot \mathrm{C}+\overline{\mathrm{D}} \cdot \overline{\mathrm{E}}$
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