Electronis Discussion
Ask us anything
Toggle navigation
GO Electronics
Email or Username
Password
Remember
Login
Register
|
I forgot my password
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
New Blog
Blogs
Exams
GATE ECE 2014 Set 2 | Question: 10
0
votes
14
views
In CMOS technology, shallow P-well or N-well regions can be formed using
low pressure chemical vapour deposition
low energy sputtering
low temperature dry oxidation
low energy ion-implantation
gate2014-ec-2
electronic-devices
cmos
asked
Mar 26, 2018
in
Electronic Devices
by
Milicevic3306
(
15.8k
points)
recategorized
Nov 15, 2020
by
soujanyareddy13
|
14
views
answer
comment
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
0
Answers
← Prev Question
Next Question →
← Prev. Qn. in Cat.
Next Qn. in Cat. →
Answer:
D
Exact tag match
Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.
1,174
questions
78
answers
11
comments
43,916
users
