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The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset $(\overline{R_{d}}\:\text{input}).$ The counter corresponding to this circuit is

  1. a modulo-$5$ binary up counter
  2. a modulo-$6$ binary down counter
  3. a modulo-$5$ binary down counter
  4. a modulo-$6$ binary up counter
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