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For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero.

If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a

1. $\text{mod}-5\:\text{counter}$
2. $\text{mod}-6\:\text{counter}$
3. $\text{mod}-7\:\text{counter}$
4. $\text{mod}-8\:\text{counter}$

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