Recent questions and answers in Sequential Circuits / GO Electronics

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GATE ECE 2010 | Question: 37
Assuming that all flip-flops are in reset condition initially, the count sequence observed at $\text{Q}_\text{A}$ in the circuit shown is $0010111 \ldots$ $0001011 \ldots$ $0101111 \ldots$ $0110100 \ldots$

Assuming that all flip-flops are in reset condition initially, the count sequence observed at $\text{Q}_\text{A}$ in the circuit shown is$0010111 \ldots$$0001011 \ldots$$...

minimalist

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minimalist answered Dec 27, 2023

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GATE ECE 2011 | Question: 41
Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarrow 11 \rightarrow 01 \rightarrow 10 \rightarrow 00 \rightarrow \cdots$ The connections to the ...

Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarro...

admin

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admin asked Sep 3, 2022

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GATE ECE 2017 Set 1 | Question: 17
Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.

Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ ha...

admin

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admin asked Nov 17, 2017