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Most viewed questions in Analog Circuits
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41
GATE ECE 2014 Set 1 | Question: 10
If fixed positive charges are present in the gate oxide of an $n$-channel enhancement type MOSFET, it will lead to a decrease in the threshold voltage channel length modulation an increase in substrate leakage current an increase in accumulation capacitance
If fixed positive charges are present in the gate oxide of an $n$-channel enhancement type MOSFET, it will lead to a decrease in the threshold voltagechannel length modul...
Milicevic3306
16.0k
points
152
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Milicevic3306
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Mar 25, 2018
Analog Circuits
gate2014-ec-1
analog-circuits
mosfet
+
–
0
votes
0
answers
42
GATE ECE 2015 Set 2 | Question: 13
In the bistable circuit shown, the ideal opamp has saturation levels of $\pm\: 5\: V.$ The value of $R_{1} \text{(in}\: k\Omega)$ that gives a hysteresis width of $500\: mV$ is ________.
In the bistable circuit shown, the ideal opamp has saturation levels of $\pm\: 5\: V.$ The value of $R_{1} \text{(in}\: k\Omega)$ that gives a hysteresis width of $500\: ...
Milicevic3306
16.0k
points
147
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Milicevic3306
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Mar 27, 2018
Analog Circuits
gate2015-ec-2
numerical-answers
analog-circuits
op-amps
+
–
0
votes
0
answers
43
GATE ECE 2015 Set 3 | Question: 12
In the circuit shown using an ideal opamp, the $3$-dB cut-off frequency (in Hz) is _______.
In the circuit shown using an ideal opamp, the $3$-dB cut-off frequency (in Hz) is _______.
Milicevic3306
16.0k
points
146
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Milicevic3306
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Mar 27, 2018
Analog Circuits
gate2015-ec-3
numerical-answers
analog-circuits
op-amps
+
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0
votes
0
answers
44
GATE ECE 2014 Set 1 | Question: 37
In the voltage regulator circuit shown in the figure, the op-amp is ideal. The BJT has $V_{BE} = 0.7\:V$ and $\beta = 100,$ and the zener voltage is $4.7\:V.$ For a regulated output of $9\:V,$ the value of $R$ (in $\Omega)$ is ______.
In the voltage regulator circuit shown in the figure, the op-amp is ideal. The BJT has $V_{BE} = 0.7\:V$ and $\beta = 100,$ and the zener voltage is $4.7\:V.$ For a regul...
Milicevic3306
16.0k
points
145
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Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
numerical-answers
analog-circuits
op-amps
bipolar-junction-transistor
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0
votes
0
answers
45
GATE ECE 2015 Set 3 | Question: 9
In the circuit shown, the voltage $V_{X}$ (in Volts) is ________.
In the circuit shown, the voltage $V_{X}$ (in Volts) is ________.
Milicevic3306
16.0k
points
144
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Milicevic3306
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Mar 27, 2018
Analog Circuits
gate2015-ec-3
analog-circuits
+
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0
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0
answers
46
GATE ECE 2013 | Question: 42
In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is $+5 V, X$ and $Y$ are digital signals with $0\: V$ as logic $0$ and $V_{cc}$ as logic $1,$ then the Boolean expression for $Z$ is $XY$ $\overline{X}Y$ $X\overline{Y}$ $\overline{XY}$
In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}...
Milicevic3306
16.0k
points
143
views
Milicevic3306
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Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
diodes
+
–
0
votes
0
answers
47
GATE ECE 2012 | Question: 50
In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at every p-n junction is $10\:nm$. The relative permittivities of $Si$ and $SiO_2$, respectively, are ... $0.7\:fF$ $0.7\:pF$ $0.35\:fF$ $0.24\:pF$
In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at ev...
Milicevic3306
16.0k
points
143
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Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
mos-transistor
+
–
0
votes
0
answers
48
GATE ECE 2017 Set 2 | Question: 10
An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then the effective base width increases and common-emitter current gain ... width decreases and common-emitter current gain increases the effective base width decreases and common-emitter current gain decreases
An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then the effective base...
admin
46.4k
points
142
views
admin
asked
Nov 23, 2017
Analog Circuits
gate2017-ec-2
bipolar-junction-transistor
analog-circuits
+
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0
votes
0
answers
49
GATE ECE 2015 Set 1 | Question: 42
In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\circ}C$, the value of the voltage $V_{12}=V_1 - V_2$ (in mV) is _______.
In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\c...
Milicevic3306
16.0k
points
141
views
Milicevic3306
asked
Mar 27, 2018
Diode Circuits
gate2015-ec-1
numerical-answers
+
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0
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0
answers
50
GATE ECE 2017 Set 1 | Question: 35
In the circuit shown, the voltage $V_{IN}(t)$ is described by: $V_{IN}(t)=\begin{cases} 0, & \text{for } t< 0 \\ 15 \text{Volts} & \text{for } t\geq 0 \end{cases}$ where $t$ is in seconds. The time (in seconds) at which the current $I$ in the circuit will reach the value $2$ Amperes is ___________.
In the circuit shown, the voltage $V_{IN}(t)$ is described by: $$V_{IN}(t)=\begin{cases} 0, & \text{for } t< 0 \\ 15 \text{Volts} & \text{for } t\geq 0 \end{cases}$$wher...
admin
46.4k
points
141
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
numerical-answers
analog-circuits
+
–
0
votes
0
answers
51
GATE ECE 2014 Set 2 | Question: 12
In the differential amplifier shown in the figure, the magnitude of the common-mode and differential-mode gains are $A_{CM}$ and $A_{d},$ respectively. If the resistance $R_{E}$ is increased, then $A_{cm}$ increases common-mode rejection ratio increases $A_{d}$ increases common-mode rejection ratio decreases
In the differential amplifier shown in the figure, the magnitude of the common-mode and differential-mode gains are $A_{CM}$ and $A_{d},$ respectively. If the resistance ...
Milicevic3306
16.0k
points
140
views
Milicevic3306
asked
Mar 26, 2018
Analog Circuits
gate2014-ec-2
analog-circuits
amplifier
+
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0
votes
0
answers
52
GATE ECE 2014 Set 1 | Question: 34
A BJT is biased in forward active mode. Assume $V_{EE} = 0.7\:V, \: kT/q = 25\:mV$ and reverse saturation current $I_{S} = 10^{-13}\:A.$ The transconductance of the BJT (in $mA/V$) is __________
A BJT is biased in forward active mode. Assume $V_{EE} = 0.7\:V, \: kT/q = 25\:mV$ and reverse saturation current $I_{S} = 10^{-13}\:A.$ The transconductance of the BJT ...
Milicevic3306
16.0k
points
140
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
numerical-answers
bipolar-junction-transistor
analog-circuits
+
–
0
votes
0
answers
53
GATE ECE 2016 Set 2 | Question: 12
A long-channel $NMOS$ transistor is biased in the linear region with $V_{DS}=50$ $m$ $V$ and is used as a resistance. Which one of the following statement is $NOT$ correct? If the device width $W$ is increased, the resistance ... decreases. If the device length $L$ is increased, the resistance increases. If $V_{GS}$ is incresed, the resistance increases.
A long-channel $NMOS$ transistor is biased in the linear region with $V_{DS}=50$ $m$ $V$ and is used as a resistance. Which one of the following statement is $NOT$ correc...
Milicevic3306
16.0k
points
139
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
54
GATE ECE 2014 Set 2 | Question: 9
An increase in the base recombination of a BJT will increase the common emitter dc current gain $\beta$ the breakdown voltage $BV_{CEO}$ the unity-gain cut-off frequency $f_{T}$ the transconductance $g_{m}$
An increase in the base recombination of a BJT will increasethe common emitter dc current gain $\beta$the breakdown voltage $BV_{CEO}$the unity-gain cut-off frequency $f_...
Milicevic3306
16.0k
points
139
views
Milicevic3306
asked
Mar 26, 2018
Analog Circuits
gate2014-ec-2
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
55
GATE ECE 2016 Set 1 | Question: 31
A network consisting of a finite number of linear resistor (R), inductor (L), and capacitor (C) elements, connected all in series or all in parallel, is excited with a source of the form ... $\sum_{k=1}^{3} a_k\cos(k\omega_0t+\phi_k) \\$ $\sum_{k=1}^{2} a_k\cos(k\omega_0t+\phi_k)$
A network consisting of a finite number of linear resistor (R), inductor (L), and capacitor (C) elements, connected all in series or all in parallel, is excited with a so...
Milicevic3306
16.0k
points
137
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-1
analog-circuits
impedance
+
–
0
votes
0
answers
56
GATE ECE 2014 Set 4 | Question: 35
Consider two BJTs biased at the same collector current with area $A_1=0.2 \mu m \times 0.2 \mu m$ and $A_2 = 300 \mu m \times 300 \mu m$. Assuming that all other device parameters are identical, $kT/q=26 \: mV$, the intrinsic carrier concentration ... $V_{BE1}-V_{BE2})$ is ________.
Consider two BJTs biased at the same collector current with area $A_1=0.2 \mu m \times 0.2 \mu m$ and $A_2 = 300 \mu m \times 300 \mu m$. Assuming that all other device p...
Milicevic3306
16.0k
points
134
views
Milicevic3306
asked
Mar 26, 2018
Analog Circuits
gate2014-ec-4
numerical-answers
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
57
GATE ECE 2014 Set 1 | Question: 13
In the low-pass filter shown in the figure, for a cut-off frequency of $5\:kHz,$ the value of $R_{2}\:(\text{in}\:k\Omega)$ is ______.
In the low-pass filter shown in the figure, for a cut-off frequency of $5\:kHz,$ the value of $R_{2}\:(\text{in}\:k\Omega)$ is ______.
Milicevic3306
16.0k
points
134
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Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
numerical-answers
analog-circuits
low-pass-filters
+
–
0
votes
0
answers
58
GATE ECE 2013 | Question: 43
A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is $\sin \omega t$ $(\sin \omega t \:+ \mid \sin \omega t \mid)/2$ $(\sin \omega t \: - \mid \sin \omega t \mid)/2$ $0$ for all $t$
A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is $\sin \omega t$$(\sin...
Milicevic3306
16.0k
points
133
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
diodes
+
–
0
votes
0
answers
59
GATE ECE 2013 | Question: 41
In the circuit shown below the $\text{op-amps}$ are ideal. Then $V_{\text{out}}$ in $\text{Volts}$ is $4$ $6$ $8$ $10$
In the circuit shown below the $\text{op-amps}$ are ideal. Then $V_{\text{out}}$ in $\text{Volts}$ is$4$$6$$8$$10$
Milicevic3306
16.0k
points
131
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
electronic-devices
+
–
0
votes
0
answers
60
GATE ECE 2017 Set 2 | Question: 14
Consider the circuit shown in the figure. Assume base-to-emitter voltage $V_{BE}=0.8 V$ and common-base current gain ($\alpha$) of the transistor is unity. The value of the collector-to-emitter voltage $V_{CE}$ (in volt) is ____________
Consider the circuit shown in the figure. Assume base-to-emitter voltage $V_{BE}=0.8 V$ and common-base current gain ($\alpha$) of the transistor is unity. The value of t...
admin
46.4k
points
131
views
admin
asked
Nov 23, 2017
Analog Circuits
gate2017-ec-2
bipolar-junction-transistor
numerical-answers
analog-circuits
+
–
0
votes
0
answers
61
GATE ECE 2016 Set 1 | Question: 14
The following signal $V_i$ of peak voltage $8 \: V$ is applied to the non-inverting terminal of an ideal Op-amp.The transistor has $V_{EE}=0.7 \: V$, $\beta=100; \: V_{LED}=1.5 \: V$, $V_{CC}=10 \: V$ and $ – V_{CC}= – 10 \:V$. The number of times the LED glows is ________
The following signal $V_i$ of peak voltage $8 \: V$ is applied to the non-inverting terminal of an ideal Op-amp.The transistor has $V_{EE}=0.7 \: V$, $\beta=100; \: V_{LE...
Milicevic3306
16.0k
points
128
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-1
numerical-answers
analog-circuits
op-amps
+
–
0
votes
0
answers
62
GATE ECE 2018 | Question: 43
In the circuit shown below, the $(W/L)$ value for $M_{2}$ is twice that for $M_{1}$. The two $\text{nMOS}$ transistors are otherwise identical. The threshold voltage $V_{T}$ for both transistors is $1.0\:V$. Note that $V_{GS}$ for $M_{2}$ ... $V_{x}$ is ________.
In the circuit shown below, the $(W/L)$ value for $M_{2}$ is twice that for $M_{1}$. The two $\text{nMOS}$ transistors are otherwise identical. The threshold voltage $V_{...
gatecse
1.6k
points
128
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
63
GATE ECE 2015 Set 2 | Question: 40
Assuming that the opamp in the circuit shown below is ideal, the output voltage ܸ$V_{o}$ (in volts) is________.
Assuming that the opamp in the circuit shown below is ideal, the output voltage ܸ$V_{o}$ (in volts) is________.
Milicevic3306
16.0k
points
127
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2015-ec-2
numerical-answers
analog-circuits
op-amps
+
–
0
votes
0
answers
64
GATE ECE 2017 Set 1 | Question: 41
For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that the emitter and collector currents are equal. Given that $V_{T}=25mV,V_{BE}=0.7V$, and the BJT output resistance $r_{o}$ is practically infinite. Under these conditions, the midband voltage gain magnitude, $A_{v}=\mid v_{o}/v_{i} \mid $, V/V is ____________.
For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that the emitter and collector currents are equal. Given that $V_{T}=25mV,V...
admin
46.4k
points
126
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
bjt-and-mosfet-amplifiers
numerical-answers
analog-circuits
+
–
0
votes
0
answers
65
GATE ECE 2016 Set 2 | Question: 46
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}.$ The positive value of $k$ for which the gain margin of the loop is exactly $0$ dB and the phase margin of the loop is exactly zero degree is _________
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}.$ The positive v...
Milicevic3306
16.0k
points
123
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
feedback
+
–
0
votes
0
answers
66
GATE ECE 2018 | Question: 33
The distance (in meters) a wave has to propagate in a medium having a skin depth of $0.1\:m$ so that the amplitude of the wave attenuates by $20\:dB$, is $0.12$ $0.23$ $0.46$ $2.3$
The distance (in meters) a wave has to propagate in a medium having a skin depth of $0.1\:m$ so that the amplitude of the wave attenuates by $20\:dB$, is $0.12$$0.23$$0.4...
gatecse
1.6k
points
123
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
analog-circuits
+
–
0
votes
0
answers
67
GATE ECE 2016 Set 2 | Question: 7
The switch has been in position $1$ for a long time and abruptly changes to position $2$ at $t = 0$. If time $t$ is in seconds, the capacitor voltage $V_{C}$ (in volts) for $t > 0$ is given by $4\left ( 1- \text{ exp }\left ( -t/0.5 \right ) \right )$ ... $4\left ( 1-\text{ exp }\left ( -t/0.6 \right ) \right )$ $10 -6 \text{ exp }\left ( -t/0.6 \right )$
The switch has been in position $1$ for a long time and abruptly changes to position $2$ at $t = 0$. If time $t$ is in seconds, the...
Milicevic3306
16.0k
points
121
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
analog-circuits
+
–
0
votes
0
answers
68
GATE ECE 2016 Set 2 | Question: 41
An opamp has a finite open loop voltage gain of $100$. Its input offset voltage $V_{ios}(=+5mV)$ is modeled as shown in the circuit below. The amplifier is ideal in all other respects. $V_{\text{input}}$ is $25 \: mV$. The output voltage (in millivolts) is _________
An opamp has a finite open loop voltage gain of $100$. Its input offset voltage $V_{ios}(=+5mV)$ is modeled as shown in the circuit below. The amplifier is ideal in all o...
Milicevic3306
16.0k
points
120
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
op-amps
+
–
1
votes
0
answers
69
GATE ECE 2015 Set 3 | Question: 34
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be $1\: mA$ at a drain-source voltage of $5\: V.$ When the drain-source voltage was increased to $6\: V$ while keeping gate-source voltage same, the ... the applied drain-source voltage. The channel length modulation parameter $\lambda\:(\text{in}\: V^{-1})$ is _______.
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be $1\: mA$ at a drain-source voltage of $5\: V.$ When the drain-source volta...
Milicevic3306
16.0k
points
120
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2015-ec-3
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
70
GATE ECE 2014 Set 4 | Question: 13
The circuit shown represents a bandpass filter a voltage controlled oscillator an amplitude modulator a monostable multivibrator
The circuit shown representsa bandpass filtera voltage controlled oscillatoran amplitude modulatora monostable multivibrator
Milicevic3306
16.0k
points
119
views
Milicevic3306
asked
Mar 26, 2018
Analog Circuits
gate2014-ec-4
analog-circuits
oscillator
+
–
0
votes
0
answers
71
GATE ECE 2016 Set 3 | Question: 21
For a superheterodyne receiver, the intermediate frequency is $15\ MHz$ and the local oscillator frequency is $3.5\ GHz$. If the frequency of the received signal is greater than the local oscillator frequency, then the image frequency (in $MHz$) is _______
For a superheterodyne receiver, the intermediate frequency is $15\ MHz$ and the local oscillator frequency is $3.5\ GHz$. If the frequency of the received signal is great...
Milicevic3306
16.0k
points
117
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-3
numerical-answers
analog-circuits
oscillator
+
–
0
votes
0
answers
72
GATE ECE 2016 Set 1 | Question: 15
Consider the oscillator circuit shown in the figure. The function of the network (shown in dotted lines) consisting of the $100 \: k \Omega$ resistor in series with the two diodes connected back-to-back is to: introduce amplitude ... circuit to oscillate at a single frequency. enable the loop gain to take on a value that produces square wave oscillations.
Consider the oscillator circuit shown in the figure. The function of the network (shown in dotted lines) consisting of the $100 \: k \Omega$ resistor in series with the t...
Milicevic3306
16.0k
points
117
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-1
analog-circuits
oscillator
+
–
0
votes
0
answers
73
GATE ECE 2014 Set 3 | Question: 11
The desirable characteristics of a transconductance amplifier are high input resistance and high output resistance high input resistance and low output resistance low input resistance and high output resistance low input resistance and low output resistance
The desirable characteristics of a transconductance amplifier are high input resistance and high output resistancehigh input resistance and low output resistancelow input...
Milicevic3306
16.0k
points
115
views
Milicevic3306
asked
Mar 26, 2018
Analog Circuits
gate2014-ec-3
amplifier
analog-circuits
+
–
0
votes
0
answers
74
GATE ECE 2014 Set 1 | Question: 39
For the amplifier shown in the figure, the BJT parameters are $V_{BE} = 0.7\:V, \beta = 200,$ and thermal voltage $V_{T} = 25\:mV.$ The voltage gain $(v_{0}/v_{i})$ of the amplifier is ______.
For the amplifier shown in the figure, the BJT parameters are $V_{BE} = 0.7\:V, \beta = 200,$ and thermal voltage $V_{T} = 25\:mV.$ The voltage gain $(v_{0}/v_{i})$ of th...
Milicevic3306
16.0k
points
114
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
numerical-answers
analog-circuits
bjt-and-mosfet-amplifiers
+
–
0
votes
0
answers
75
GATE ECE 2015 Set 1 | Question: 11
For the circuit with ideal diodes shown in the figure, the shape of the output $v_{\text{out}}$ for the given sine wave input $v_{\text{in}}$ will be
For the circuit with ideal diodes shown in the figure, the shape of the output $v_{\text{out}}$ for the given sine wave input $v_{\text{in}}$ will be
Milicevic3306
16.0k
points
113
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2015-ec-1
analog-circuits
diodes
+
–
0
votes
0
answers
76
GATE ECE 2016 Set 2 | Question: 11
The Ebers-Moll model of a $BJT$ is valid only in active mode only in active and saturation modes only in active and cut-off modes in active, saturation and cut-off modes
The Ebers-Moll model of a $BJT$ is valid only in active modeonly in active and saturation modesonly in active and cut-off modesin active, saturation and cut-off modes
Milicevic3306
16.0k
points
110
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
analog-circuits
bipolar-junction-transistor
+
–
0
votes
0
answers
77
GATE ECE 2017 Set 1 | Question: 39
In the figure shown, the $npn$ transistor acts as a switch. For the input $V_{in}(t)$ as shown in the figure, the transistor switches between the cut-off and saturation regions of operation, when $T$ is large. Assume collector-to-emitter ... $(\alpha)$ of the transistor for the switching should be __________.
In the figure shown, the $npn$ transistor acts as a switch.For the input $V_{in}(t)$ as shown in the figure, the transistor switches between the cut-off and saturation re...
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Analog Circuits
gate2017-ec-1
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numerical-answers
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GATE ECE 2016 Set 1 | Question: 33
An AC voltage source $V = 10 \sin(t)$ volts is applied to the following network. Assume that $R_1 = 3 k\Omega$, $R_2 = 6 k\Omega$ and $R_3 = 9k\Omega$, and that the diode is ideal. RMS current $I_{rms}$(in mA) through the diode is _______
An AC voltage source $V = 10 \sin(t)$ volts is applied to the following network. Assume that $R_1 = 3 k\Omega$, $R_2 = 6 k\Omega$ and $R_3 = 9k\Omega$, and that the diode...
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GATE ECE 2015 Set 3 | Question: 9
Which one of the following processes is preferred to form the gate dielectric $(SiO_{2})$ of MOSFETs ? Sputtering Molecular beam epitaxy Wet oxidation Dry oxidation
Which one of the following processes is preferred to form the gate dielectric $(SiO_{2})$ of MOSFETs ? Sputtering Molecular beam epitaxy Wet oxidation Dry oxidation
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Analog Circuits
gate2015-ec-3
analog-circuits
mosfet
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80
GATE ECE 2015 Set 3 | Question: 40
In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics:$k_{n} ݇ = \mu _{n}C_{ox}(W/L) = 1\:mA/V^{2};V_{TN} = 1V.$ Assume that the channel length modulation parameter $\lambda$ is zero ... supply voltage ܸ$V_{DD}$ (in volts) needed to ensure that transistor $M_{1}$ operates in saturation mode of operation is _______.
In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics:$k_{n} ݇ = \mu _{n}C_{ox}(W/L) = 1\:mA/V^{2};V_{TN} = 1V.$ Assume tha...
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