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Highest voted questions in Analog Circuits
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81
GATE ECE 2014 Set 1 | Question: 37
In the voltage regulator circuit shown in the figure, the op-amp is ideal. The BJT has $V_{BE} = 0.7\:V$ and $\beta = 100,$ and the zener voltage is $4.7\:V.$ For a regulated output of $9\:V,$ the value of $R$ (in $\Omega)$ is ______.
In the voltage regulator circuit shown in the figure, the op-amp is ideal. The BJT has $V_{BE} = 0.7\:V$ and $\beta = 100,$ and the zener voltage is $4.7\:V.$ For a regul...
Milicevic3306
16.0k
points
142
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
numerical-answers
analog-circuits
op-amps
bipolar-junction-transistor
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–
0
votes
0
answers
82
GATE ECE 2014 Set 1 | Question: 38
In the circuit shown the op-amp has finite input impedance, infinite voltage gain, and zero input offset voltage. The output voltage $V_{out}$ is $-I_{2}(R_{1} + R_{2})$ $I_{2}R_{2}$ $I_{1}R_{2}$ $-I_{1}(R_{1} + R_{2})$
In the circuit shown the op-amp has finite input impedance, infinite voltage gain, and zero input offset voltage. The output voltage $V_{out}$ is $-I_{2}(R_{1} + R_{2})$$...
Milicevic3306
16.0k
points
104
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
op-amps
analog-circuits
electronic-devices
+
–
0
votes
0
answers
83
GATE ECE 2014 Set 1 | Question: 39
For the amplifier shown in the figure, the BJT parameters are $V_{BE} = 0.7\:V, \beta = 200,$ and thermal voltage $V_{T} = 25\:mV.$ The voltage gain $(v_{0}/v_{i})$ of the amplifier is ______.
For the amplifier shown in the figure, the BJT parameters are $V_{BE} = 0.7\:V, \beta = 200,$ and thermal voltage $V_{T} = 25\:mV.$ The voltage gain $(v_{0}/v_{i})$ of th...
Milicevic3306
16.0k
points
112
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2014-ec-1
numerical-answers
analog-circuits
bjt-and-mosfet-amplifiers
+
–
0
votes
0
answers
84
GATE ECE 2013 | Question: 42
In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is $+5 V, X$ and $Y$ are digital signals with $0\: V$ as logic $0$ and $V_{cc}$ as logic $1,$ then the Boolean expression for $Z$ is $XY$ $\overline{X}Y$ $X\overline{Y}$ $\overline{XY}$
In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}...
Milicevic3306
16.0k
points
140
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
diodes
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–
0
votes
0
answers
85
GATE ECE 2013 | Question: 43
A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is $\sin \omega t$ $(\sin \omega t \:+ \mid \sin \omega t \mid)/2$ $(\sin \omega t \: - \mid \sin \omega t \mid)/2$ $0$ for all $t$
A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is $\sin \omega t$$(\sin...
Milicevic3306
16.0k
points
130
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
diodes
+
–
0
votes
0
answers
86
GATE ECE 2013 | Question: 41
In the circuit shown below the $\text{op-amps}$ are ideal. Then $V_{\text{out}}$ in $\text{Volts}$ is $4$ $6$ $8$ $10$
In the circuit shown below the $\text{op-amps}$ are ideal. Then $V_{\text{out}}$ in $\text{Volts}$ is$4$$6$$8$$10$
Milicevic3306
16.0k
points
130
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
electronic-devices
+
–
0
votes
0
answers
87
GATE ECE 2013 | Question: 4
In a forward biased $pn$ junction diode, the sequence of events that best describes the mechanism of current flow is injection, and subsequent diffusion and recombination of minority carriers injection, and subsequent drift and ... , and subsequent diffusion and generation of minority carriers extraction, and subsequent drift and recombination of minority carriers
In a forward biased $pn$ junction diode, the sequence of events that best describes the mechanism of current flow is injection, and subsequent diffusion and recombination...
Milicevic3306
16.0k
points
103
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2013-ec
analog-circuits
diodes
+
–
0
votes
0
answers
88
GATE ECE 2012 | Question: 50
In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at every p-n junction is $10\:nm$. The relative permittivities of $Si$ and $SiO_2$, respectively, are ... $0.7\:fF$ $0.7\:pF$ $0.35\:fF$ $0.24\:pF$
In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at ev...
Milicevic3306
16.0k
points
133
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
mos-transistor
+
–
0
votes
0
answers
89
GATE ECE 2012 | Question: 51
In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at every p-n junction is $10\:nm$. The relative permittivities of $Si$ and $SiO_2$, respectively, are ... $2\:fF$ $7\:fF$ $2\:pF$ $7\:pF$
In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at ev...
Milicevic3306
16.0k
points
78
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
mos-transistor
+
–
0
votes
0
answers
90
GATE ECE 2012 | Question: 44
The voltage gain $A_v$ of the circuit shown below is $\mid A_v \mid\approx 200$ $\mid A_v\mid \approx 100$ $ \mid A_v \mid \approx 20$ $\mid A_v \mid \approx 10$
The voltage gain $A_v$ of the circuit shown below is$\mid A_v \mid\approx 200$$\mid A_v\mid \approx 100$$ \mid A_v \mid \approx 20$$\mid A_v \mid \approx 10$
Milicevic3306
16.0k
points
89
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
+
–
0
votes
0
answers
91
GATE ECE 2012 | Question: 29
The input $x(t)$ and output $y(t)$ of a system are related as $y(t)=\underset{-\infty}{\int}x(\tau)\cos(3\tau)d\tau$. The system is time-invariant and stable stable and not time-invariant time-invariant and not stable not time-invariant and not stable
The input $x(t)$ and output $y(t)$ of a system are related as $y(t)=\underset{-\infty}{\int}x(\tau)\cos(3\tau)d\tau$. The system istime-invariant and stablestable and not...
Milicevic3306
16.0k
points
77
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
+
–
0
votes
0
answers
92
GATE ECE 2012 | Question: 30
The feedback system shown below oscillates at $2\:rad/s$ when $K=2$ and $a=0.75$ $K=3$ and $a=0.75$ $K=4$ and $a=0.5$ $K=2$ and $a=0.5$
The feedback system shown below oscillates at $2\:rad/s$ when$K=2$ and $a=0.75$$K=3$ and $a=0.75$$K=4$ and $a=0.5$$K=2$ and $a=0.5$
Milicevic3306
16.0k
points
87
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
oscillator
+
–
0
votes
0
answers
93
GATE ECE 2012 | Question: 33
Assuming both the voltage sources are in phase, the value of $R$ for which maximum power is transferred from circuit $A$ to circuit $B$ is $0.8\:\Omega$ $1.4\:\Omega$ $2\:\Omega$ $2.8\:\Omega$
Assuming both the voltage sources are in phase, the value of $R$ for which maximum power is transferred from circuit $A$ to circuit $B$ is$0.8\:\Omega$$1.4\:\Omega$$2\:\O...
Milicevic3306
16.0k
points
74
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
+
–
0
votes
0
answers
94
GATE ECE 2012 | Question: 13
The diodes and capacitors in the circuit shown are ideal. The voltage $v(t)$ across the diode $D1$ is $\cos(\omega t)-1$ $\sin(\omega t)$ $1-\cos(\omega t)$ $1-\sin(\omega t)$
The diodes and capacitors in the circuit shown are ideal. The voltage $v(t)$ across the diode $D1$ is$\cos(\omega t)-1$$\sin(\omega t)$$1-\cos(\omega t)$$1-\sin(\omega t)...
Milicevic3306
16.0k
points
88
views
Milicevic3306
asked
Mar 25, 2018
Analog Circuits
gate2012-ec
analog-circuits
+
–
0
votes
0
answers
95
GATE ECE 2018 | Question: 37
A $dc$ current of $26\:\mu A$ flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, the diode has a junction capacitance of $0.5\:nF$. Its neutral region ... $\mu A$, correct to one decimal place) is __________.
A $dc$ current of $26\:\mu A$ flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, th...
gatecse
1.6k
points
302
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
+
–
0
votes
0
answers
96
GATE ECE 2018 | Question: 38
An op-amp based circuit is implemented as shown below. In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place) at node $A$, connected to the negative input of the op-amp as indicated in the figure is ________.
An op-amp based circuit is implemented as shown below. In the above circuit, assume the op-amp to be ideal. The voltage (in volt...
gatecse
1.6k
points
209
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
op-amps
+
–
0
votes
0
answers
97
GATE ECE 2018 | Question: 43
In the circuit shown below, the $(W/L)$ value for $M_{2}$ is twice that for $M_{1}$. The two $\text{nMOS}$ transistors are otherwise identical. The threshold voltage $V_{T}$ for both transistors is $1.0\:V$. Note that $V_{GS}$ for $M_{2}$ ... $V_{x}$ is ________.
In the circuit shown below, the $(W/L)$ value for $M_{2}$ is twice that for $M_{1}$. The two $\text{nMOS}$ transistors are otherwise identical. The threshold voltage $V_{...
gatecse
1.6k
points
125
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
nmos-transistor
+
–
0
votes
0
answers
98
GATE ECE 2018 | Question: 32
A $2\times 2$ ROM array is built with the help of diodes as shown in the circuit below. Here $W0$ and $W1$ are signals that select the word lines and $B0$ and $B1$ are signals that are output of the sense amps based on the stored data corresponding to the ... $\begin{bmatrix} 1 &0 \\ 1&0 \end{bmatrix}$ $\begin{bmatrix} 1 &1 \\ 0&0 \end{bmatrix}$
A $2\times 2$ ROM array is built with the help of diodes as shown in the circuit below. Here $W0$ and $W1$ are signals that select the word lines and $B0$ and $B1$ are si...
gatecse
1.6k
points
241
views
gatecse
asked
Feb 19, 2018
Diode Circuits
gate2018-ec
digital-circuits
rom
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–
0
votes
0
answers
99
GATE ECE 2018 | Question: 33
The distance (in meters) a wave has to propagate in a medium having a skin depth of $0.1\:m$ so that the amplitude of the wave attenuates by $20\:dB$, is $0.12$ $0.23$ $0.46$ $2.3$
The distance (in meters) a wave has to propagate in a medium having a skin depth of $0.1\:m$ so that the amplitude of the wave attenuates by $20\:dB$, is $0.12$$0.23$$0.4...
gatecse
1.6k
points
120
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
analog-circuits
+
–
0
votes
0
answers
100
GATE ECE 2018 | Question: 35
For the circuit given in the figure, the voltage $V_{c}$ (in volts) across the capacitor is $1.25\sqrt{2}\sin\left ( 5t-0.25\pi \right )$ $1.25\sqrt{2}\sin\left ( 5t-0.125\pi \right )$ $2.5\sqrt{2}\sin\left ( 5t-0.25\pi \right )$ $2.5\sqrt{2}\sin\left ( 5t-0.125\pi \right )$
For the circuit given in the figure, the voltage $V_{c}$ (in volts) across the capacitor is $1.25\sqrt{2}\sin\left ( 5t-0.25\pi \...
gatecse
1.6k
points
103
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
analog-circuits
+
–
0
votes
0
answers
101
GATE ECE 2018 | Question: 36
For the circuit given in the figure, the magnitude of the loop current (in amperes, correct to three decimal places) $0.5$ second after closing the switch is _______.
For the circuit given in the figure, the magnitude of the loop current (in amperes, correct to three decimal places) $0.5$ second after closing the switch is _______.
gatecse
1.6k
points
177
views
gatecse
asked
Feb 19, 2018
Analog Circuits
gate2018-ec
numerical-answers
analog-circuits
+
–
0
votes
0
answers
102
GATE ECE 2017 Set 2 | Question: 40
Assuming that transistors $M_1$ and $M_2$ are identical and have a threshold voltage of $1$ V, the state of transistors $M_1$ and $M_2$ are respectively Saturation, Saturation Linear, Linear Linear, Saturation Saturation, Linear
Assuming that transistors $M_1$ and $M_2$ are identical and have a threshold voltage of $1$ V, the state of transistors $M_1$ and $M_2$ are respectivelySaturation, Satura...
admin
46.4k
points
102
views
admin
asked
Nov 25, 2017
Analog Circuits
gate2017-ec-2
transistor
analog-circuits
+
–
0
votes
0
answers
103
GATE ECE 2017 Set 2 | Question: 41
In the circuit shown, transistors $Q_1$ and $Q_2$ are biased at a collector current of $2.6$ mA. Assuming that transistor current gains are sufficiently large to assume collector current equal to emitter current and thermal voltage of $26$ mV, the magnitude of voltage gain $V_0/V_s$ in the mid-band frequency range is __________(up to second decimal place).
In the circuit shown, transistors $Q_1$ and $Q_2$ are biased at a collector current of $2.6$ mA. Assuming that transistor current gains are sufficiently large to assume c...
admin
46.4k
points
163
views
admin
asked
Nov 25, 2017
Analog Circuits
gate2017-ec-2
bipolar-junction-transistor
numerical-answers
analog-circuits
+
–
0
votes
0
answers
104
GATE ECE 2017 Set 2 | Question: 42
In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors $Q_1, Q_2, \dots ,Q_{32}$ are identical in all respects and have infinitely large values of common-emitter current gain $(\beta)$. The collector current $(Ic)$ ... is $0.7$ V and the thermal voltage $V_T = 26$ mV. The output voltage $V_{out}$ (in volts) is ______________
In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors $Q_1, Q_2, \dots ,Q_{32}$ are identical in all respects and have infinitely...
admin
46.4k
points
187
views
admin
asked
Nov 25, 2017
Analog Circuits
gate2017-ec-2
op-amps
numerical-answers
analog-circuits
+
–
0
votes
0
answers
105
GATE ECE 2017 Set 2 | Question: 37
For a particular intensity of incident light on a silicon $pn$ junction solar cell, the photocurrent density $(J_L)$ is $2.5 mA/cm^2$ and the open-circuit voltage ($V_{oc}$) is $0.451$ V. Consider thermal voltage ($V_T$) to ... the incident light is increased by $20$ times, assuming that the temperature remains unchanged, $V_{oc}$ (in volts) will be ____________
For a particular intensity of incident light on a silicon $pn$ junction solar cell, the photocurrent density $(J_L)$ is $2.5 mA/cm^2$ and the open-circuit voltage ($V_{oc...
admin
46.4k
points
105
views
admin
asked
Nov 25, 2017
Analog Circuits
gate2017-ec-2
p-n-junction
numerical-answers
analog-circuits
+
–
0
votes
0
answers
106
GATE ECE 2017 Set 2 | Question: 38
Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double that of T1. Both the transistors are biased in the saturation region of operation, but the gate overdrive voltage ($V_{GS}-V_{TH}$ ... $2g_{m1}$ $8I_{D1}$ and $4g_{m1}$ $4I_{D1}$ and $4g_{m1}$ $4I_{D1}$ and $2g_{m1}$
Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double that of T1. Both the transistors are biased in the saturation region...
admin
46.4k
points
258
views
admin
asked
Nov 25, 2017
Analog Circuits
gate2017-ec-2
mosfet
biasing
analog-circuits
+
–
0
votes
0
answers
107
GATE ECE 2017 Set 2 | Question: 14
Consider the circuit shown in the figure. Assume base-to-emitter voltage $V_{BE}=0.8 V$ and common-base current gain ($\alpha$) of the transistor is unity. The value of the collector-to-emitter voltage $V_{CE}$ (in volt) is ____________
Consider the circuit shown in the figure. Assume base-to-emitter voltage $V_{BE}=0.8 V$ and common-base current gain ($\alpha$) of the transistor is unity. The value of t...
admin
46.4k
points
129
views
admin
asked
Nov 23, 2017
Analog Circuits
gate2017-ec-2
bipolar-junction-transistor
numerical-answers
analog-circuits
+
–
0
votes
0
answers
108
GATE ECE 2017 Set 2 | Question: 10
An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then the effective base width increases and common-emitter current gain ... width decreases and common-emitter current gain increases the effective base width decreases and common-emitter current gain decreases
An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then the effective base...
admin
46.4k
points
141
views
admin
asked
Nov 23, 2017
Analog Circuits
gate2017-ec-2
bipolar-junction-transistor
analog-circuits
+
–
0
votes
0
answers
109
GATE ECE 2017 Set 2 | Question: 12
The output $V_0$ of the diode circuit shown in the figure is connected to an averaging DC voltmeter. The reading on the DC voltmeter in Volts, neglecting the voltage drop across the diode, is _________________.
The output $V_0$ of the diode circuit shown in the figure is connected to an averaging DC voltmeter. The reading on the DC voltmeter in Volts, neglecting the voltage drop...
admin
46.4k
points
272
views
admin
asked
Nov 23, 2017
Analog Circuits
gate2017-ec-2
diodes
numerical-answers
analog-circuits
+
–
0
votes
0
answers
110
GATE ECE 2017 Set 1 | Question: 39
In the figure shown, the $npn$ transistor acts as a switch. For the input $V_{in}(t)$ as shown in the figure, the transistor switches between the cut-off and saturation regions of operation, when $T$ is large. Assume collector-to-emitter ... $(\alpha)$ of the transistor for the switching should be __________.
In the figure shown, the $npn$ transistor acts as a switch.For the input $V_{in}(t)$ as shown in the figure, the transistor switches between the cut-off and saturation re...
admin
46.4k
points
105
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
bipolar-junction-transistor
numerical-answers
analog-circuits
+
–
0
votes
0
answers
111
GATE ECE 2017 Set 1 | Question: 41
For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage $V_{tn}=1V$ and its transconductance parameter $\mu_{n}C_{ox}\big(\frac{W}{L}\big)=1 \: mA/V^{2}$.Neglect channel length modulation and body bias effects. Under these conditions, the drain current $I_{D}$ in $mA$ is ________.
For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage $V_{tn}=1V$ and its transconductance parameter $\mu_{n}C_{ox}\big(\frac{W}{...
admin
46.4k
points
205
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
bjt-and-mosfet-amplifiers
numerical-answers
analog-circuits
+
–
0
votes
0
answers
112
GATE ECE 2017 Set 1 | Question: 41
For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that the emitter and collector currents are equal. Given that $V_{T}=25mV,V_{BE}=0.7V$, and the BJT output resistance $r_{o}$ is practically infinite. Under these conditions, the midband voltage gain magnitude, $A_{v}=\mid v_{o}/v_{i} \mid $, V/V is ____________.
For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that the emitter and collector currents are equal. Given that $V_{T}=25mV,V...
admin
46.4k
points
125
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
bjt-and-mosfet-amplifiers
numerical-answers
analog-circuits
+
–
0
votes
0
answers
113
GATE ECE 2017 Set 1 | Question: 42
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain, $A_{0}=10^{5}V/V$ and an open-loop cut-off frequency, $f_{c}=8Hz$. The voltage gain of the amplifier at $15$ kHz, in V/V, is____________.
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain, $A_{0}=10^{5}V/V$ and an o...
admin
46.4k
points
151
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
numerical-answers
analog-circuits
op-amps
+
–
0
votes
0
answers
114
GATE ECE 2017 Set 1 | Question: 20
Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?
Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?
admin
46.4k
points
274
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
mosfet
analog-circuits
+
–
0
votes
0
answers
115
GATE ECE 2017 Set 1 | Question: 35
In the circuit shown, the voltage $V_{IN}(t)$ is described by: $V_{IN}(t)=\begin{cases} 0, & \text{for } t< 0 \\ 15 \text{Volts} & \text{for } t\geq 0 \end{cases}$ where $t$ is in seconds. The time (in seconds) at which the current $I$ in the circuit will reach the value $2$ Amperes is ___________.
In the circuit shown, the voltage $V_{IN}(t)$ is described by: $$V_{IN}(t)=\begin{cases} 0, & \text{for } t< 0 \\ 15 \text{Volts} & \text{for } t\geq 0 \end{cases}$$wher...
admin
46.4k
points
139
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
numerical-answers
analog-circuits
+
–
0
votes
0
answers
116
GATE ECE 2017 Set 1 | Question: 14
The Miller effect in the context of a Common Emitter amplifier explains An increase in the low-frequency cutoff frequency An increase in the high-frequency cutoff frequency A decrease in the low-frequency cutoff frequency A decrease in the high -frequency cutoff frequency
The Miller effect in the context of a Common Emitter amplifier explainsAn increase in the low-frequency cutoff frequencyAn increase in the high-frequency cutoff frequency...
admin
46.4k
points
507
views
admin
asked
Nov 17, 2017
Analog Circuits
gate2017-ec-1
amplifier
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GATE ECE 2017 Set 1 | Question: 15
A good transconductance amplifier should have high input resistance and low output resistance low input resistance and high output resistance high input and output resistances low input and output resistances
A good transconductance amplifier should havehigh input resistance and low output resistancelow input resistance and high output resistancehigh input and output resistanc...
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Analog Circuits
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analog-circuits
amplifier
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118
GATE ECE 2017 Set 1 | Question: 11
For a narrow base PNP BJT , the excess minority carrier concentrations($\Delta n_{E}$ for emitter,$\Delta p_{B}$ for base ,$\Delta n_{c}$ for collector) normalized to equilibrium minority carrier concentrations($n_{E0}$ for ... are shown below. Which one of the following biasing modes is the transistor operating in? Forward active Satiration Inverse active Cutoff
For a narrow base PNP BJT , the excess minority carrier concentrations($\Delta n_{E}$ for emitter,$\Delta p_{B}$ for base ,$\Delta n_{c}$ for collector) normalized to eq...
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Analog Circuits
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transistor
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119
GATE ECE 2017 Set 1 | Question: 12
For the operational amplifier circuit shown, the output saturation voltage are $\pm 15 \:V$. The upper and lower threshold voltages for the circuit are,respectively, $+ 5 \: V$ and $– 5 V$ $+ 7 \: V$ and $– 3 \: V$ $+ 3 \: V$ and $- 7 \: V$ $+ 3 \: V$ and $– 3 \: V$
For the operational amplifier circuit shown, the output saturation voltage are $\pm 15 \:V$. The upper and lower threshold voltages for the circuit are,respectively,$+ 5 ...
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Analog Circuits
gate2017-ec-1
op-amps
amplifier
analog-circuits
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120
GATE ECE 2017 Set 1 | Question: 13
A good transconductance amplifier should have High input resistance and low output resistance Low input resistance and high output resistance High input and output resistance Low input and output resistance
A good transconductance amplifier should haveHigh input resistance and low output resistanceLow input resistance and high output resistanceHigh input and output resistanc...
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46.4k
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96
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Nov 17, 2017
Analog Circuits
gate2017-1mosfet
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