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GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$
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digital-circuits
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GATE ECE 2014 Set 1 | Question: 40
The output $F$ in the digital logic circuit shown in the figure is $F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$ $F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\overline{Z}$ $F = \overline{X}\:\overline{Y}\:Z + X\:Y\:Z$ $F = \overline{X}\:\overline{Y}\:\overline{Z} + X\:Y\:Z$
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gate2014-ec-1
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