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GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$
go_editor
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Number Representations
Feb 13, 2020
by
go_editor
1.9k
points
109
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gate2020-ec
digital-circuits
semiconductor
0
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0
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2
GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
Milicevic3306
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Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
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91
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gate2016-ec-3
digital-circuits
semiconductor
0
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0
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3
GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
Milicevic3306
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Number Representations
Mar 28, 2018
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Milicevic3306
15.8k
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67
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gate2016-ec-2
digital-circuits
combinational-circuits
multiplexers
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0
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4
GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
Milicevic3306
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in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
74
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gate2016-ec-2
digital-circuits
analog-to-digital-converter
0
votes
0
answers
5
GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.
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Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
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69
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gate2016-ec-1
digital-circuits
semiconductor
0
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0
answers
6
GATE ECE 2014 Set 4 | Question: 36
An N-type semiconductor having uniform doping is biased as shown in the figure. If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy level of the valance band and $E_F$ is the Fermi level, which one of the following represents the energy band diagram for the biased N-type semiconductor? .
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Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
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44
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gate2014-ec-4
digital-circuits
semiconductor
0
votes
0
answers
7
GATE ECE 2014 Set 4 | Question: 40
An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by $Y = A \: \overline{B} \:C+A \: \overline{C} \:D$ $Y = \overline{A} \: B \:C +A \: \overline{B} \: D$ $Y = A \: B \: \overline{C} + \overline{A} \: C \:D$ $Y= \overline{A} \: \overline{B} \: D + A \: \overline{B} \: C$
Milicevic3306
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Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
71
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gate2014-ec-4
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
8
GATE ECE 2014 Set 3 | Question: 16
Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit? $F= W \overline{S_1} \: \overline{S_2}$ $F= WS_1+WS_2 + S_{1}S_{2}$ $F= \overline{W}+S_{1}+S_{2}$ $F= W\oplus S_{1}\oplus S_{2}$
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Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
83
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gate2014-ec-3
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
9
GATE ECE 2017 Set 2 | Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $
admin
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Number Representations
Nov 23, 2017
by
admin
32.7k
points
152
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gate2017-ec-2
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
10
GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
admin
asked
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Number Representations
Nov 17, 2017
by
admin
32.7k
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144
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gate2017-ec-1
digital-circuits
sequential-circuit
shift-registers
numerical-answers
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