GO Electronics
Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
New Blog
Blogs
Exams
Dark Mode
Filter
Recent
Hot!
Most votes
Most answers
Most views
Previous GATE
Featured
Most answered questions in Digital Circuits
0
votes
2
answers
1
GATE ECE 2014 Set 1 | Question: 15
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to $X$ $Y$ $XY$ $X+Y$
Milicevic3306
asked
in
Digital Circuits
Mar 26, 2018
by
Milicevic3306
15.8k
points
120
views
gate2014-ec-1
digital-circuits
boolean-algebra
1
vote
2
answers
2
GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
admin
asked
in
Number Representations
Nov 25, 2017
by
admin
35.7k
points
2.4k
views
gate2017-ec-2
numerical-answers
digital-circuits
combinational-circuits
adder
0
votes
1
answer
3
GATE ECE 2020 | Question: 10
The figure below shows a multiplexer where $S_{1}$ and $S{2}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
353
views
gate2020-ec
digital-circuits
combinational-circuits
multiplexers
0
votes
1
answer
4
GATE ECE 2014 Set 1 | Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
Milicevic3306
asked
in
Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
240
views
gate2014-ec-1
digital-circuits
sequential-circuit
1
vote
1
answer
5
GATE ECE 2018 | Question: 31
A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$
gatecse
asked
in
Number Representations
Feb 19, 2018
by
gatecse
1.5k
points
241
views
gate2018-ec
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
6
GATE ECE 2021 | Question: 11
If $(1235)_{x}\:=\:(3033)_{y}$, where $x$ and $y$ indicate the bases of the corresponding numbers, then $x\:=\:7$ and $y\:=\:5$ $x\:=\:8$ and $y\:=\:6$ $x\:=\:6$ and $y\:=\:4$ $x\:=\:9$ and $y\:=\:7$
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
251
views
gateec-2021
digital-circuits
number-system
number-representation
0
votes
0
answers
7
GATE ECE 2021 | Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
112
views
gateec-2021
digital-circuits
combinational-circuits
decoders
0
votes
0
answers
8
GATE ECE 2021 | Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
266
views
gateec-2021
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
9
GATE ECE 2021 | Question: 46
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
132
views
gateec-2021
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
10
GATE ECE 2020 | Question: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from mid-bandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
120
views
gate2020-ec
digital-circuits
semiconductor
0
votes
0
answers
11
GATE ECE 2020 | Question: 19
In an $8085$ microprocessor, the number of address lines required to access a $16$ K byte memory bank is ____________ .
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
89
views
gate2020-ec
numerical-answers
digital-circuits
microprocessor-8085
0
votes
0
answers
12
GATE ECE 2020 | Question: 20
A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
111
views
gate2020-ec
numerical-answers
digital-circuits
data-converters
0
votes
0
answers
13
GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$
go_editor
asked
in
Number Representations
Feb 13, 2020
by
go_editor
1.9k
points
114
views
gate2020-ec
digital-circuits
semiconductor
1
vote
0
answers
14
GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
go_editor
asked
in
Number Representations
Feb 13, 2020
by
go_editor
1.9k
points
274
views
gate2020-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
15
GATE ECE 2019 | Question: 14
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively? $\text{0 and D}$ $\text{Hi-Z and D}$ $\text{0 and 1}$ $\text{Hi-Z and}$ $ \overline{D}$
Arjun
asked
in
Digital Circuits
Feb 12, 2019
by
Arjun
6.0k
points
115
views
gate2019-ec
digital-circuits
logic-gates
0
votes
0
answers
16
GATE ECE 2019 | Question: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR
Arjun
asked
in
Digital Circuits
Feb 12, 2019
by
Arjun
6.0k
points
117
views
gate2019-ec
digital-circuits
logic-gates
0
votes
0
answers
17
GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
99
views
gate2016-ec-3
digital-circuits
semiconductor
0
votes
0
answers
18
GATE ECE 2016 Set 3 | Question: 16
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be $4E$ and $0$ $4E$ and $1$ $4F$ and $0$ $4F$ and $1$
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
63
views
gate2016-ec-3
digital-circuits
microprocessor-8085
0
votes
0
answers
19
GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
96
views
gate2016-ec-3
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
20
GATE ECE 2016 Set 3 | Question: 18
The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is $4$ $5$ $6$ $7$
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
69
views
gate2016-ec-3
digital-circuits
combinational-circuits
logic-gates
1
vote
0
answers
21
GATE ECE 2016 Set 3 | Question: 43
Following is the K-map of a Boolean function of five variables $P,Q,R,S$ and $X$ ... $\overline{Q}\:S\:X+\;Q\:\overline{S}\:\overline{X}$ $\overline{Q}\:S+\;Q\overline{S}$
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
53
views
gate2016-ec-3
digital-circuits
k-map
min-sum-of-products-form
0
votes
0
answers
22
GATE ECE 2016 Set 3 | Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
84
views
gate2016-ec-3
numerical-answers
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
23
GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
99
views
gate2016-ec-3
digital-circuits
sequential-circuit
counters
0
votes
0
answers
24
GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
89
views
gate2016-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
25
GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
72
views
gate2016-ec-2
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
26
GATE ECE 2016 Set 2 | Question: 42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
50
views
gate2016-ec-2
digital-circuits
microprocessor
rom
0
votes
0
answers
27
GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
77
views
gate2016-ec-2
digital-circuits
analog-to-digital-converter
0
votes
0
answers
28
GATE ECE 2016 Set 2 | Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
177
views
gate2016-ec-2
digital-circuits
state-transition-diagram
0
votes
0
answers
29
GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
78
views
gate2016-ec-1
digital-circuits
semiconductor
0
votes
0
answers
30
GATE ECE 2016 Set 1 | Question: 12
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): As channel length reduces,OFF-state current increases. As channel length reduces,output resistance increases. As channel length reduces,threshold voltage remains constant. As channel ... . Which of the above statements are INCORRECT? P and Q P and S Q and R R and S
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
64
views
gate2016-ec-1
digital-circuits
semiconductor
mosfet
0
votes
0
answers
31
GATE ECE 2016 Set 1 | Question: 43
The functionality implemented by the circuit below is $2$-to-$1$ multiplexer $4$-to-$1$ multiplexer $7$-to-$1$ multiplexer $6$-to-$1$ multiplexer
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
120
views
gate2016-ec-1
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
32
GATE ECE 2016 Set 1 | Question: 44
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this? For POP, the data transceivers remain in the same direction as for instruction fetch ... in the stack pointer. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
48
views
gate2016-ec-1
digital-circuits
microprocessor-8085
0
votes
0
answers
33
GATE ECE 2015 Set 3 | Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
82
views
gate2015-ec-3
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
34
GATE ECE 2015 Set 3 | Question: 16
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$ ...
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
62
views
gate2015-ec-3
digital-circuits
microprocessor-8085
0
votes
0
answers
35
GATE ECE 2015 Set 3 | Question: 37
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
76
views
gate2015-ec-3
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
36
GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
89
views
gate2015-ec-3
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
37
GATE ECE 2015 Set 3 | Question: 49
Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit step sequence. Assume ݊$x_{2}[n]= \begin{cases} \sqrt{1.5}& \text{for } n = 0,1 \\ 0 &\text{otherwise.} \end{cases}$ Then the value of $\alpha$ is _________.
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
37
views
gate2015-ec-3
numerical-answers
digital-circuits
0
votes
0
answers
38
GATE ECE 2015 Set 2 | Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
76
views
gate2015-ec-2
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
39
GATE ECE 2015 Set 2 | Question: 15
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator? MOV B, M PCHL RNZ SBI BEH
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
66
views
gate2015-ec-2
digital-circuits
microprocessor-8085
0
votes
0
answers
40
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
126
views
gate2015-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
Page:
1
2
3
next »
Top Users
Dec 2022
Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.