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Most answered questions in Digital Circuits
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41
GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digita...
Milicevic3306
16.0k
points
217
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-2
digital-circuits
analog-to-digital-converter
+
–
0
votes
0
answers
42
GATE ECE 2016 Set 2 | Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. ...
Milicevic3306
16.0k
points
348
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-2
digital-circuits
state-transition-diagram
+
–
0
votes
0
answers
43
GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in th...
Milicevic3306
16.0k
points
147
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-1
digital-circuits
semiconductor
+
–
0
votes
0
answers
44
GATE ECE 2016 Set 1 | Question: 12
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): As channel length reduces,OFF-state current increases. As channel length reduces,output resistance increases. As channel length reduces,threshold voltage remains constant. As channel ... . Which of the above statements are INCORRECT? P and Q P and S Q and R R and S
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET):As channel length reduces,OFF-state current increases.As channel length...
Milicevic3306
16.0k
points
163
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-1
digital-circuits
semiconductor
mosfet
+
–
0
votes
0
answers
45
GATE ECE 2016 Set 1 | Question: 43
The functionality implemented by the circuit below is $2$-to-$1$ multiplexer $4$-to-$1$ multiplexer $7$-to-$1$ multiplexer $6$-to-$1$ multiplexer
The functionality implemented by the circuit below is$2$-to-$1$ multiplexer $4$-to-$1$ multiplexer$7$-to-$1$ multiplexer$6$-to-$1$ multiplexer
Milicevic3306
16.0k
points
244
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-1
digital-circuits
combinational-circuits
multiplexers
decoders
+
–
0
votes
0
answers
46
GATE ECE 2016 Set 1 | Question: 44
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this? For POP, the data transceivers remain in the same direction as for instruction fetch ... in the stack pointer. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?For POP, the data...
Milicevic3306
16.0k
points
95
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-1
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
47
GATE ECE 2015 Set 3 | Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for...
Milicevic3306
16.0k
points
186
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-3
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
48
GATE ECE 2015 Set 3 | Question: 16
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$ ...
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$$\begin{array}{ll} {} & ...
Milicevic3306
16.0k
points
106
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-3
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
49
GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the cir...
Milicevic3306
16.0k
points
189
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-3
digital-circuits
sequential-circuit
flip-flops
+
–
0
votes
0
answers
50
GATE ECE 2015 Set 3 | Question: 49
Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit step sequence. Assume ݊$x_{2}[n]= \begin{cases} \sqrt{1.5}& \text{for } n = 0,1 \\ 0 &\text{otherwise.} \end{cases}$ Then the value of $\alpha$ is _________.
Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit s...
Milicevic3306
16.0k
points
79
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-3
numerical-answers
digital-circuits
+
–
1
votes
0
answers
51
GATE ECE 2015 Set 2 | Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively,NOR, OROR, NANDNAND, ORAND,NA...
Milicevic3306
16.0k
points
153
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-2
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
52
GATE ECE 2015 Set 2 | Question: 15
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator? MOV B, M PCHL RNZ SBI BEH
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator?MOV B, MPCHLRNZSBI BEH
Milicevic3306
16.0k
points
129
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-2
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
53
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
Milicevic3306
16.0k
points
247
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
+
–
1
votes
0
answers
54
GATE ECE 2015 Set 2 | Question: 36
A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$ Which one of the product of sums given below is equal to the function $F(X, Y, Z)?$ ...
A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $$F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$$Which one of the product of sums given bel...
Milicevic3306
16.0k
points
142
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-2
digital-circuits
boolean-algebra
+
–
0
votes
0
answers
55
GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-...
Milicevic3306
16.0k
points
224
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2015-ec-2
digital-circuits
sequential-circuit
counters
+
–
0
votes
0
answers
56
GATE ECE 2015 Set 2 | Question: 38
A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$-to-$4$ ... $D_{in}, S_{0}, S_{1}, S_{2} $ $D_{in}, S_{2}, S_{0}, S_{1}$
A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the e...
Milicevic3306
16.0k
points
167
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-2
digital-circuits
combinational-circuits
decoders
+
–
0
votes
0
answers
57
GATE ECE 2015 Set 1 | Question: 14
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively B and F A and F H and F A and C
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectivelyB and FA and FH and FA and C
Milicevic3306
16.0k
points
102
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-1
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
58
GATE ECE 2015 Set 1 | Question: 15
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ___________
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of addr...
Milicevic3306
16.0k
points
127
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-1
numerical-answers
digital-circuits
decoders
+
–
0
votes
0
answers
59
GATE ECE 2015 Set 1 | Question: 16
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog value (in Volts) corresponding to the digital signal $1111$ is _________
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog ...
Milicevic3306
16.0k
points
122
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-1
numerical-answers
digital-circuits
+
–
1
votes
0
answers
60
GATE ECE 2015 Set 1 | Question: 36
The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ ... $(X+\overline{Y}+\overline{Z})(\overline{X}+Y+Z)(\overline{X}+\overline{Y}+Z)(X + Y + Z)$
The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ converted into the canonica...
Milicevic3306
16.0k
points
94
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2015-ec-1
boolean-algebra
digital-circuits
+
–
0
votes
0
answers
61
GATE ECE 2014 Set 4 | Question: 14
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then droop rate decreases and acquisition time decreases droop rate decreases and acquisition time increases droop rate increases and acquisition time decreases droop rate increases and acquisition time increases
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, thendroop rate decreases and acquisition time decreasesdroop rate decreases and acqu...
Milicevic3306
16.0k
points
69
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-4
digital-circuits
sample-and-hold-circuits
+
–
1
votes
0
answers
62
GATE ECE 2014 Set 4 | Question: 15
In the circuit shown in the figure, if $C=0$, the expression for $Y$ is $Y=A \overline{B} + \overline{A}B$ $Y=A+B$ $Y=\overline{A} + \overline{B}$ $Y=A \: B$
In the circuit shown in the figure, if $C=0$, the expression for $Y$ is$Y=A \overline{B} + \overline{A}B$$Y=A+B$$Y=\overline{A} + \overline{B}$$Y=A \: B$
Milicevic3306
16.0k
points
135
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-4
digital-circuits
combinational-circuits
logic-gates
+
–
0
votes
0
answers
63
GATE ECE 2014 Set 4 | Question: 16
The output $(Y)$ of the circuit shown in the figure is $\overline{A} + \overline{B} +C$ $A + \overline{B} \cdot \overline{C} + A \cdot \overline{C}$ $\overline{A} +B+\overline{C}$ $A \cdot B \cdot \overline{C}$
The output $(Y)$ of the circuit shown in the figure is$\overline{A} + \overline{B} +C$$A + \overline{B} \cdot \overline{C} + A \cdot \overline{C}$$\overline{A} +B+\overli...
Milicevic3306
16.0k
points
138
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-4
digital-circuits
+
–
0
votes
0
answers
64
GATE ECE 2014 Set 4 | Question: 36
An N-type semiconductor having uniform doping is biased as shown in the figure. If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy level of the valance band and $E_F$ is the Fermi level, which one of the following represents the energy band diagram for the biased N-type semiconductor?
An N-type semiconductor having uniform doping is biased as shown in the figure.If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy lev...
Milicevic3306
16.0k
points
93
views
Milicevic3306
asked
Mar 26, 2018
Number Representations
gate2014-ec-4
digital-circuits
semiconductor
+
–
0
votes
0
answers
65
GATE ECE 2014 Set 4 | Question: 42
An $8085$ microprocessor executes $ STA 1234H $ with starting address location $1FFEH$ (STA copies the contents of the Accumulator to the $16$ ... $1FH, FEH, 1FH, FFH, 12H$ $1FH, 1FH, 12H, 12H$ $1FH, 1FH, 12H, 20H, 12H$
An $8085$ microprocessor executes $“STA 1234H”$ with starting address location $1FFEH$ (STA copies the contents of the Accumulator to the $16$- bit address location)....
Milicevic3306
16.0k
points
72
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-4
digital-circuits
microprocessor-8085
+
–
0
votes
0
answers
66
GATE ECE 2014 Set 3 | Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch Master-Slave D Flip Flop
The circuit shown in the figure is a Toggle Flip FlopJK Flip FlopSR LatchMaster-Slave D Flip Flop
Milicevic3306
16.0k
points
162
views
Milicevic3306
asked
Mar 26, 2018
Number Representations
gate2014-ec-3
digital-circuits
sequential-circuit
flip-flops
+
–
1
votes
0
answers
67
GATE ECE 2014 Set 3 | Question: 16
Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit? $F= W \overline{S_1} \: \overline{S_2}$ $F= WS_1+WS_2 + S_{1}S_{2}$ $F= \overline{W}+S_{1}+S_{2}$ $F= W\oplus S_{1}\oplus S_{2}$
Consider the multiplexer based logic circuit shown in the figure.Which one of the following Boolean functions is realized by the circuit?$F= W \overline{S_1} \: \overline...
Milicevic3306
16.0k
points
342
views
Milicevic3306
asked
Mar 26, 2018
Number Representations
gate2014-ec-3
digital-circuits
combinational-circuits
multiplexers
+
–
0
votes
0
answers
68
GATE ECE 2014 Set 3 | Question: 40
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
Milicevic3306
16.0k
points
131
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-3
digital-circuits
sram
+
–
1
votes
0
answers
69
GATE ECE 2014 Set 3 | Question: 41
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by $F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$ $F= W\overline{X}+\overline{W}X+\overline{Y}Z$ $F= W\overline{X}\overline{Y}+\overline{W}X\overline{Y}$ $F= ( \overline{W}+\overline{X} )\overline{Y}\overline{Z}$
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by$F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$$F= W\overline{X}+\ov...
Milicevic3306
16.0k
points
194
views
Milicevic3306
asked
Mar 26, 2018
Number Representations
gate2014-ec-3
digital-circuits
combinational-circuits
multiplexers
+
–
1
votes
0
answers
70
GATE ECE 2014 Set 3 | Question: 42
If $X$ and $Y$ are inputs and the Difference $(D=X-Y)$ and the Borrow $(B)$ are the outputs, which one of the following diagrams implements a half-subtractor?
If $X$ and $Y$ are inputs and the Difference $(D=X-Y)$ and the Borrow $(B)$ are the outputs, which one of the following diagrams implements a half-subtractor?
Milicevic3306
16.0k
points
139
views
Milicevic3306
asked
Mar 26, 2018
Number Representations
gate2014-ec-3
digital-circuits
combinational-circuits
half-subtractor-circuit
multiplexers
+
–
0
votes
0
answers
71
GATE ECE 2014 Set 3 | Question: 54
A region shown below contains a perfect conducting half-space and air. The surface current $\overrightarrow{K_{s}}$ on the surface of the perfect conductor is $\overrightarrow{K_{s}}= \hat{x}2$ amperes per meter. The tangential $\overrightarrow{H}$ field in the ... per meter $\hat{x}2$ amperes per meter $-\hat{z}2$ amperes per meter $\hat{z}2$ amperes per meter
A region shown below contains a perfect conducting half-space and air. The surface current $\overrightarrow{K_{s}}$ on the surface of the perfect conductor is $\overright...
Milicevic3306
16.0k
points
171
views
Milicevic3306
asked
Mar 26, 2018
Number Representations
gate2014-ec-3
digital-circuits
+
–
0
votes
0
answers
72
GATE ECE 2014 Set 2 | Question: 16
In a half-subtractor circuit with $X$ and $Y$ as inputs, the Borrow $(M)$ and Difference $(N = X – Y)$ are given by $M = X \oplus Y, \: \: \: N = XY$ $M = XY, \: \: \:N = X \oplus Y$ $M = \overline{ X}Y, \: \: \: N =X \oplus Y$ $M = X \overline{ Y}, \: \: \: N = \overline{X \oplus Y}$
In a half-subtractor circuit with $X$ and $Y$ as inputs, the Borrow $(M)$ and Difference $(N = X – Y)$ are given by$M = X \oplus Y, \: \: \: N = XY$$M = XY, \: \: \:N ...
Milicevic3306
16.0k
points
137
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-2
digital-circuits
combinational-circuits
half-subtractor-circuit
+
–
0
votes
0
answers
73
GATE ECE 2014 Set 2 | Question: 17
As FIR system is described by the system function $ H(z) = 1 + \frac{7}{2} z^{-1} + \frac{3}{2}z^{-2}$. The system is maximum phase minimum phase mixed phase zero phase
As FIR system is described by the system function $$ H(z) = 1 + \frac{7}{2} z^{-1} + \frac{3}{2}z^{-2}$$. The system ismaximum phaseminimum phasemixed phasezero phase
Milicevic3306
16.0k
points
120
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-2
digital-circuits
+
–
0
votes
0
answers
74
GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots...
Milicevic3306
16.0k
points
146
views
Milicevic3306
asked
Mar 26, 2018
Combinational Circuits
gate2014-ec-2
digital-circuits
sequential-circuit
flip-flops
+
–
0
votes
0
answers
75
GATE ECE 2014 Set 2 | Question: 42
For the $8085$ microprocessor, the interfacing circuit to input $8$-bit digital data $( DI_{0}-DI_{7})$ from an external device is shown in the figure. The instruction for correct data transfer is $\text{MVI A, F8H}$ $\text{IN F8H}$ $\text{OUT F8H}$ $\text{LDA F8F8H}$
For the $8085$ microprocessor, the interfacing circuit to input $8$-bit digital data $( DI_{0}-DI_{7})$ from an external device is shown in the figure. The instruction fo...
Milicevic3306
16.0k
points
166
views
Milicevic3306
asked
Mar 26, 2018
Digital Circuits
gate2014-ec-2
digital-circuits
combinational-circuits
microprocessor-8085
+
–
0
votes
0
answers
76
GATE ECE 2014 Set 1 | Question: 16
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of th...
Milicevic3306
16.0k
points
236
views
Milicevic3306
asked
Mar 25, 2018
Number Representations
gate2014-ec-1
numerical-answers
flip-flops
digital-circuits
+
–
2
votes
0
answers
77
GATE ECE 2014 Set 1 | Question: 40
The output $F$ in the digital logic circuit shown in the figure is $F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$ $F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\overline{Z}$ $F = \overline{X}\:\overline{Y}\:Z + X\:Y\:Z$ $F = \overline{X}\:\overline{Y}\:\overline{Z} + X\:Y\:Z$
The output $F$ in the digital logic circuit shown in the figure is$F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$$F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\over...
Milicevic3306
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Milicevic3306
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Mar 25, 2018
Combinational Circuits
gate2014-ec-1
digital-circuits
combinational-circuits
logic-gates
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0
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78
GATE ECE 2013 | Question: 45
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ ... $0500H-08FFH, 1500H-18FFH, 3500H-38FFH, 5500H-58FFH$ $0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH$
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ respectively are mapp...
Milicevic3306
16.0k
points
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Mar 25, 2018
Digital Circuits
gate2013-ec
digital-circuits
semiconductor
ram
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0
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0
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79
GATE ECE 2013 | Question: 32
Two magnetically uncoupled inductive coils have $Q$ factors $q_{1}$ and $q_{2}$ at the chosen operating frequency. Their respective resistances are $R_{1}$ and $R_{2}.$ When connected in series, their effective $Q$ factor at the same operating frequency is $q_{1} + q_{2}$ ... $(q_{1}R_{2} + q_{2}R_{1})/(R_{1} + R_{2})$
Two magnetically uncoupled inductive coils have $Q$ factors $q_{1}$ and $q_{2}$ at the chosen operating frequency. Their respective resistances are $R_{1}$ and $R_{2}.$ W...
Milicevic3306
16.0k
points
113
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Mar 25, 2018
Digital Circuits
gate2013-ec
digital-circuits
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0
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0
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80
GATE ECE 2013 | Question: 12
For $8085$ microprocessor, the following program is executed. $\begin{array}{ll} & MVI\: A, 05H; \\ & MVI\: B, 05H; \\ PTR: & ADD \:B; \\ & DCR \:B; \\ & JNZ\: PTR; \\ & ADI\: 03H; \\ & HLT; \end{array}$ At the end of program, accumulator contains $17H$ $20H $ $23H$ $ 05H$
For $8085$ microprocessor, the following program is executed.$\begin{array}{ll} & MVI\: A, 05H; \\ & MVI\: B, 05H; \\ PTR: & ADD \:B; \\ & DCR \:B; \\ & JNZ\: PTR; \\ & ...
Milicevic3306
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98
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Mar 25, 2018
Digital Circuits
gate2013-ec
digital-circuits
microprocessor-8085
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