GO Electronics
Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
New Blog
Blogs
Exams
Dark Mode
Filter
Recent
Hot!
Most votes
Most answers
Most views
Previous GATE
Featured
Most viewed questions in Digital Circuits
1
vote
2
answers
1
GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
admin
asked
in
Number Representations
Nov 25, 2017
by
admin
35.7k
points
2.4k
views
gate2017-ec-2
numerical-answers
digital-circuits
combinational-circuits
adder
0
votes
1
answer
2
GATE ECE 2020 | Question: 10
The figure below shows a multiplexer where $S_{1}$ and $S{2}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
353
views
gate2020-ec
digital-circuits
combinational-circuits
multiplexers
1
vote
0
answers
3
GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
go_editor
asked
in
Number Representations
Feb 13, 2020
by
go_editor
1.9k
points
274
views
gate2020-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
4
GATE ECE 2021 | Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
266
views
gateec-2021
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
5
GATE ECE 2017 Set 1 | Question: 16
The clock frequency of an $8085$ microprocessor is $5$ MHz . If the time required to execute an instruction is $1.4 \: \mu s$, then the number of T-states needed for executing the instruction is $1$ $6$ $7$ $8$
admin
asked
in
Digital Circuits
Nov 17, 2017
by
admin
35.7k
points
262
views
gate2017-ec-1
microprocessor-8085
digital-circuits
0
votes
0
answers
6
GATE ECE 2021 | Question: 11
If $(1235)_{x}\:=\:(3033)_{y}$, where $x$ and $y$ indicate the bases of the corresponding numbers, then $x\:=\:7$ and $y\:=\:5$ $x\:=\:8$ and $y\:=\:6$ $x\:=\:6$ and $y\:=\:4$ $x\:=\:9$ and $y\:=\:7$
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
251
views
gateec-2021
digital-circuits
number-system
number-representation
1
vote
1
answer
7
GATE ECE 2018 | Question: 31
A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$
gatecse
asked
in
Number Representations
Feb 19, 2018
by
gatecse
1.5k
points
241
views
gate2018-ec
digital-circuits
combinational-circuits
multiplexers
0
votes
1
answer
8
GATE ECE 2014 Set 1 | Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
Milicevic3306
asked
in
Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
240
views
gate2014-ec-1
digital-circuits
sequential-circuit
0
votes
0
answers
9
GATE ECE 2017 Set 2 | Question: 43
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is $S_0$. If the input sequence is $10101101001101$, starting with the left-most bit, then the number of times 'Out' will be $1$ is ____________
admin
asked
in
Number Representations
Nov 25, 2017
by
admin
35.7k
points
222
views
gate2017-ec-2
fsm
numerical-answers
digital-circuits
0
votes
0
answers
10
GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
35.7k
points
197
views
gate2017-ec-1
digital-circuits
sequential-circuit
counters
0
votes
0
answers
11
GATE ECE 2016 Set 2 | Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
177
views
gate2016-ec-2
digital-circuits
state-transition-diagram
1
vote
0
answers
12
GATE ECE 2017 Set 2 | Question: 45
A programmable logic array (PLA) is shown in the figure. The Boolean function $F$ implemented is $\overline{P} \: \overline{Q}R+ \overline{P}QR+P \overline{Q} \: \overline{R}$ $(\overline{P}+\overline{Q}+R)(\overline{P}+Q+R)(P+\overline{Q}+\overline{R})$ ... $(\overline{P}+\overline{Q}+R)(\overline{P}+Q+R)(P+\overline{Q}+R)$
admin
asked
in
Digital Circuits
Nov 25, 2017
by
admin
35.7k
points
176
views
gate2017-ec-2
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
13
GATE ECE 2017 Set 2 | Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $
admin
asked
in
Number Representations
Nov 23, 2017
by
admin
35.7k
points
167
views
gate2017-ec-2
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
14
GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
35.7k
points
150
views
gate2017-ec-1
digital-circuits
sequential-circuit
shift-registers
numerical-answers
0
votes
0
answers
15
GATE ECE 2017 Set 1 | Question: 45
The following FIVE instructions were executed on an $8085$ microprocessor. MVI A, $33$H MVI B, $78$H ADD B CMA ANI $32$H The Accumulator value immediately after the execution of the fifth instruction is $00H$ $10H$ $11H$ $32H$
admin
asked
in
Digital Circuits
Nov 17, 2017
by
admin
35.7k
points
138
views
gate2017-ec-1
digital-circuits
microprocessor-8085
0
votes
0
answers
16
GATE ECE 2021 | Question: 46
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
132
views
gateec-2021
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
17
GATE ECE 2017 Set 1 | Question: 17
Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.
admin
asked
in
Sequential Circuits
Nov 17, 2017
by
admin
35.7k
points
132
views
gate2017-ec-1
digital-circuits
sequential-circuit
latch
0
votes
0
answers
18
GATE ECE 2018 | Question: 47
The logic gates shown in the digital circuit below use strong pull-down $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes ... values of $X_{3}X_{2}X_{1}X_{0}$ (out of the $16$ possible values) that give $Y=1$ is ________.
gatecse
asked
in
Number Representations
Feb 19, 2018
by
gatecse
1.5k
points
128
views
gate2018-ec
numerical-answers
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
19
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
126
views
gate2015-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
20
GATE ECE 2014 Set 1 | Question: 16
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.
Milicevic3306
asked
in
Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
123
views
gate2014-ec-1
numerical-answers
flip-flops
digital-circuits
0
votes
0
answers
21
GATE ECE 2018 | Question: 46
In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.
gatecse
asked
in
Number Representations
Feb 19, 2018
by
gatecse
1.5k
points
122
views
gate2018-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
22
GATE ECE 2020 | Question: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from mid-bandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
120
views
gate2020-ec
digital-circuits
semiconductor
0
votes
0
answers
23
GATE ECE 2016 Set 1 | Question: 43
The functionality implemented by the circuit below is $2$-to-$1$ multiplexer $4$-to-$1$ multiplexer $7$-to-$1$ multiplexer $6$-to-$1$ multiplexer
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
120
views
gate2016-ec-1
digital-circuits
combinational-circuits
multiplexers
0
votes
2
answers
24
GATE ECE 2014 Set 1 | Question: 15
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to $X$ $Y$ $XY$ $X+Y$
Milicevic3306
asked
in
Digital Circuits
Mar 26, 2018
by
Milicevic3306
15.8k
points
120
views
gate2014-ec-1
digital-circuits
boolean-algebra
0
votes
0
answers
25
GATE ECE 2019 | Question: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR
Arjun
asked
in
Digital Circuits
Feb 12, 2019
by
Arjun
6.0k
points
117
views
gate2019-ec
digital-circuits
logic-gates
0
votes
0
answers
26
GATE ECE 2019 | Question: 14
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively? $\text{0 and D}$ $\text{Hi-Z and D}$ $\text{0 and 1}$ $\text{Hi-Z and}$ $ \overline{D}$
Arjun
asked
in
Digital Circuits
Feb 12, 2019
by
Arjun
6.0k
points
115
views
gate2019-ec
digital-circuits
logic-gates
0
votes
0
answers
27
GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$
go_editor
asked
in
Number Representations
Feb 13, 2020
by
go_editor
1.9k
points
114
views
gate2020-ec
digital-circuits
semiconductor
0
votes
0
answers
28
GATE ECE 2013 | Question: 45
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ ... $0500H-08FFH, 1500H-18FFH, 3500H-38FFH, 5500H-58FFH$ $0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH$
Milicevic3306
asked
in
Digital Circuits
Mar 26, 2018
by
Milicevic3306
15.8k
points
113
views
gate2013-ec
digital-circuits
semiconductor
ram
0
votes
0
answers
29
GATE ECE 2021 | Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
112
views
gateec-2021
digital-circuits
combinational-circuits
decoders
0
votes
0
answers
30
GATE ECE 2020 | Question: 20
A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.
go_editor
asked
in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
111
views
gate2020-ec
numerical-answers
digital-circuits
data-converters
0
votes
0
answers
31
GATE ECE 2017 Set 2 | Question: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR
admin
asked
in
Number Representations
Nov 23, 2017
by
admin
35.7k
points
106
views
gate2017-ec-2
logic-gates
digital-circuits
0
votes
0
answers
32
GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
35.7k
points
106
views
gate2017-ec-1
digital-circuits
sequential-circuit
latch
0
votes
0
answers
33
GATE ECE 2015 Set 2 | Question: 38
A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$-to-$4$ ... $D_{in}, S_{0}, S_{1}, S_{2} $ $D_{in}, S_{2}, S_{0}, S_{1}$
Milicevic3306
asked
in
Digital Circuits
Mar 28, 2018
by
Milicevic3306
15.8k
points
104
views
gate2015-ec-2
digital-circuits
combinational-circuits
decoders
0
votes
0
answers
34
GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
100
views
gate2015-ec-2
digital-circuits
sequential-circuit
counters
0
votes
0
answers
35
GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
99
views
gate2016-ec-3
digital-circuits
semiconductor
0
votes
0
answers
36
GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
99
views
gate2016-ec-3
digital-circuits
sequential-circuit
counters
0
votes
0
answers
37
GATE ECE 2014 Set 3 | Question: 41
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by $F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$ $F= W\overline{X}+\overline{W}X+\overline{Y}Z$ $F= W\overline{X}\overline{Y}+\overline{W}X\overline{Y}$ $F= ( \overline{W}+\overline{X} )\overline{Y}\overline{Z}$
Milicevic3306
asked
in
Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
98
views
gate2014-ec-3
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
38
GATE ECE 2018 | Question: 45
A junction is made between $p^{-Si}$ with doping density $N_{A1}=10^{15}cm^{-3}$ and $p^{Si}$ with doping density $N_{A2}=10^{17}cm^{-3}.$ Given: Boltzmann constant $k=1.38\times 10^{-23}J\cdot K^{-1},$ electronic charge ... the magnitude of the built-in potential (in volts, correct to two decimal places) across this junction will be __________.
gatecse
asked
in
Digital Circuits
Feb 19, 2018
by
gatecse
1.5k
points
98
views
gate2018-ec
numerical-answers
boltzman-constant
doping
digital-circuits
0
votes
0
answers
39
GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
96
views
gate2016-ec-3
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
40
GATE ECE 2014 Set 2 | Question: 15
The number of bytes required to represent the decimal number $1856357$ in packed BCD (Binary Coded Decimal) form is ___________.
Milicevic3306
asked
in
Digital Circuits
Mar 26, 2018
by
Milicevic3306
15.8k
points
96
views
gate2014-ec-2
digital-circuits
number-system
number-representation
Page:
1
2
3
next »
Top Users
Dec 2022
Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.