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Recent questions in Digital Circuits
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81
GATE ECE 2018 | Question: 8
The logic function $f(X, Y)$ realized by the given circuit is NOR AND NAND XOR
gatecse
asked
in
Digital Circuits
Feb 19, 2018
by
gatecse
1.5k
points
91
views
gate2018-ec
digital-circuits
combinational-circuits
logic-gates
1
vote
0
answers
82
GATE ECE 2017 Set 2 | Question: 45
A programmable logic array (PLA) is shown in the figure. The Boolean function $F$ implemented is $\overline{P} \: \overline{Q}R+ \overline{P}QR+P \overline{Q} \: \overline{R}$ $(\overline{P}+\overline{Q}+R)(\overline{P}+Q+R)(P+\overline{Q}+\overline{R})$ ... $(\overline{P}+\overline{Q}+R)(\overline{P}+Q+R)(P+\overline{Q}+R)$
admin
asked
in
Digital Circuits
Nov 25, 2017
by
admin
36.1k
points
176
views
gate2017-ec-2
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
83
GATE ECE 2017 Set 2 | Question: 43
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is $S_0$. If the input sequence is $10101101001101$, starting with the left-most bit, then the number of times 'Out' will be $1$ is ____________
admin
asked
in
Number Representations
Nov 25, 2017
by
admin
36.1k
points
222
views
gate2017-ec-2
fsm
numerical-answers
digital-circuits
1
vote
2
answers
84
GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
admin
asked
in
Number Representations
Nov 25, 2017
by
admin
36.1k
points
2.4k
views
gate2017-ec-2
numerical-answers
digital-circuits
combinational-circuits
adder
0
votes
0
answers
85
GATE ECE 2017 Set 2 | Question: 17
In a DRAM, periodic refreshing is not required information is stored in a capacitor information is stored in a latch both read and write operations can be performed simultaneously
admin
asked
in
Digital Circuits
Nov 23, 2017
by
admin
36.1k
points
69
views
gate2017-ec-2
semiconductor
digital-circuits
0
votes
0
answers
86
GATE ECE 2017 Set 2 | Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $
admin
asked
in
Number Representations
Nov 23, 2017
by
admin
36.1k
points
167
views
gate2017-ec-2
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
87
GATE ECE 2017 Set 2 | Question: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR
admin
asked
in
Number Representations
Nov 23, 2017
by
admin
36.1k
points
106
views
gate2017-ec-2
logic-gates
digital-circuits
0
votes
0
answers
88
GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
36.1k
points
197
views
gate2017-ec-1
digital-circuits
sequential-circuit
counters
0
votes
0
answers
89
GATE ECE 2017 Set 1 | Question: 45
The following FIVE instructions were executed on an $8085$ microprocessor. MVI A, $33$H MVI B, $78$H ADD B CMA ANI $32$H The Accumulator value immediately after the execution of the fifth instruction is $00H$ $10H$ $11H$ $32H$
admin
asked
in
Digital Circuits
Nov 17, 2017
by
admin
36.1k
points
138
views
gate2017-ec-1
digital-circuits
microprocessor-8085
0
votes
0
answers
90
GATE ECE 2017 Set 1 | Question: 43
Which one of the following gives the simplified sum of products expression for the Boolean function $F=m_{0}+m_{2}+m_{3}+m_{5}$, where $m_{0},m_{2},m_{3}$ and $m_{5}$ are minterms corresponding to the inputs $A,B$ and $C$ with $A$ as the $MSB$ and ... $\overline{A} BC+\overline{A} \: \overline{C}+A \overline{B}C$
admin
asked
in
Digital Circuits
Nov 17, 2017
by
admin
36.1k
points
57
views
gate2017-ec-1
digital-circuits
boolean-algebra
0
votes
0
answers
91
GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
36.1k
points
150
views
gate2017-ec-1
digital-circuits
sequential-circuit
shift-registers
numerical-answers
0
votes
0
answers
92
GATE ECE 2017 Set 1 | Question: 17
Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.
admin
asked
in
Sequential Circuits
Nov 17, 2017
by
admin
36.1k
points
132
views
gate2017-ec-1
digital-circuits
sequential-circuit
latch
0
votes
0
answers
93
GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
36.1k
points
106
views
gate2017-ec-1
digital-circuits
sequential-circuit
latch
0
votes
0
answers
94
GATE ECE 2017 Set 1 | Question: 16
The clock frequency of an $8085$ microprocessor is $5$ MHz . If the time required to execute an instruction is $1.4 \: \mu s$, then the number of T-states needed for executing the instruction is $1$ $6$ $7$ $8$
admin
asked
in
Digital Circuits
Nov 17, 2017
by
admin
36.1k
points
262
views
gate2017-ec-1
microprocessor-8085
digital-circuits
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