Hot questions in Electronic Devices / GO Electronics

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GATE ECE 2020 | Question: 31
A one-sided abrupt $pn$ junction diode has a depletion capacitance $C_{D}$ of $50$ $\text{pF}$ at a reverse bias of $0.2 V$. The plot of $1/C^{2}_{D}$ versus the applied voltage $V$ for this diode is a straight line as shown in the figure below. The slope of the plot is ___________ $\times 10^{20}F^{-2}V^{-1}$. $-5.7$ $-3.8$ $-1.2$ $-0.4$

A one-sided abrupt $pn$ junction diode has a depletion capacitance $C_{D}$ of $50$ $\text{pF}$ at a reverse bias of $0.2 V$. The plot of $1/C^{2}_{D}$ versus the applied ...

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GATE ECE 2020 | Question: 7
Consider the recombination process via bulk traps in a forward biased $pn$ homojunction diode. The maximum recombination rate is $U_{\text{max}}$ ... bias. With all other parameters unchanged, $U_{\text{max}}$ increases if the thermal velocity of the carriers increases.

Consider the recombination process via bulk traps in a forward biased $pn$ homojunction diode. The maximum recombination rate is $U_{\text{max}}$. If the electron and the...

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GATE ECE 2020 | Question: 36
An enhancement $\text{MOSFET}$ of threshold voltage $3\:V$ is being used in the sample and hold circuit given below. Assume that the substrate of the $\text{MOS}$ device is connected to $-10\:V$. If the input voltage $V_{1}$ lies between $\pm 10\:V,$ the minimum and the maximum ... $\text{10 V and -10 V}$. $\text{13 V and -7 V}$. $\text{10 V and -13 V}$.

An enhancement $\text{MOSFET}$ of threshold voltage $3\:V$ is being used in the sample and hold circuit given below. Assume that the substrate of the $\text{MOS}$ device ...

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GATE ECE 2020 | Question: 34
A $pn$ junction solar cell of area $1.0\:cm^{2}$, illuminated uniformly with $100\:mW\:cm^{-2}$, has the following parameters: Efficiency $= 15\%$, open circuit voltage $= 0.7\:V$, fill factor $= 0.8$, and thickness $=200 \mu m$ ... $0.84\times 10^{19}.$ $5.57\times 10^{19}.$ $1.04\times 10^{19}.$ $83.60\times 10^{19}.$

A $pn$ junction solar cell of area $1.0\:cm^{2}$, illuminated uniformly with $100\:mW\:cm^{-2}$, has the following parameters: Efficiency $= 15\%$, open circuit voltage $...

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GATE ECE 2019 | Question: 11
What is the electric flux $\left(\int \vec{E}.d \hat{a}\right)$ through a quarter-cylinder of height $H$ (as shown in the figure) due to an infinitely long line charge along the axis of the cylinder with a charge density of $Q?$ $\frac{HQ}{\varepsilon_{0}}$ $\frac{HQ}{4\varepsilon_{0}}$ $\frac{H\varepsilon_{0}}{4Q}$ $\frac{4H}{Q\varepsilon_{0}}$

What is the electric flux $\left(\int \vec{E}.d \hat{a}\right)$ through a quarter-cylinder of height $H$ (as shown in the figure) due to an infinitely long line charge al...

Arjun

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GATE ECE 2019 | Question: 9
The correct circuit representation of the structure shown in the figure is

The correct circuit representation of the structure shown in the figure is

Arjun

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GATE ECE 2019 | Question: 41
The $\text{RC}$ circuit shown below has a variable resistance $R(t)$ given by the following expression: $R(t)=R_{0}\left(1-\frac{t}{T}\right) \text{for} \:\: 0 \leq t < T$ where $R_{0}=1\: \Omega,$ and $C=1\:F.$ ... $t=0$ is $1\: A,$ then the current $I(t)$, in amperes, at time $t=T/2$ is __________ (rounded off to $2$ decimal places).

The $\text{RC}$ circuit shown below has a variable resistance $R(t)$ given by the following expression:$$R(t)=R_{0}\left(1-\frac{t}{T}\right) \text{for} \:\: 0 \leq t < T...

Arjun

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8

GATE ECE 2019 | Question: 13
A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin $NM_{L}$ and the HIGH noise margin $NM_{H}$? ... . $NM_{L}$ decreases and $NM_{H}$ increases. Both $NM_{L}$ and $NM_{H}$ increases. No change in the noise margins.

A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would ...

Arjun

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9

GATE ECE 2019 | Question: 10
The figure shows the high-frequency C-V curve of a MOS capacitor $(\text{at}\: T=300\: K)$ with $\Phi_{ms}= 0\: V$ and no oxide charges. The flat-band, inversion, and accumulation conditions are represented, respectively, by the points $P,Q,R$ $Q,R,P$ $R,P,Q$ $Q,P,R$

The figure shows the high-frequency C-V curve of a MOS capacitor $(\text{at}\: T=300\: K)$ with $\Phi_{ms}= 0\: V$ and no oxide charges. The flat-band, inversion, and acc...

Arjun

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10

GATE ECE 2019 | Question: 49
In an ideal $pn$ junction with an ideality factor of $1$ at $T=300\:K,$ the magnitude of the reverse-bias voltage required to reach $75\%$ of its reverse saturation current, rounded off to $2$ decimal places, is ______ $mV.$ $[k=1.38 \times 10^{-23} JK^{-1}, h=6.625 \times 10^{-34} J-s, q=1.602 \times 10^{-19}C]$

In an ideal $pn$ junction with an ideality factor of $1$ at $T=300\:K,$ the magnitude of the reverse-bias voltage required to reach $75\%$ of its reverse saturation curre...

Arjun

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11

GATE ECE 2019 | Question: 8
Which one of the following options describes correctly the equilibrium band diagram at $T=300\:K$ of a Silicon $pnn^{+}\:\:p^{++}$ configuration shown in the figure?

Which one of the following options describes correctly the equilibrium band diagram at $T=300\:K$ of a Silicon $pnn^{+}\:\:p^{++}$ configuration shown in the figure?

Arjun

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12

GATE ECE 2019 | Question: 52
In the circuit shown. $V_{s}$ is a $10\:V$ square wave of period, $T=4\: ms$ with $R=500\: \Omega$ and $C= 10\:\mu F.$ The capacitor is initially uncharged at $t=0,$ and the diode is assumed to be ideal. The voltage across the capacitor $(V_{c})$ at $3\:ms$ is equal to _____ volts (rounded off to one decimal place)

In the circuit shown. $V_{s}$ is a $10\:V$ square wave of period, $T=4\: ms$ with $R=500\: \Omega$ and $C= 10\:\mu F.$ The capacitor is initially uncharged at $t=0,$ and ...

Arjun

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13

GATE ECE 2019 | Question: 38
In the circuit shown, the breakdown voltage and the maximum current of the Zener diode are $20\:V$ and $60\:mA$, respectively. The values of $R_{1}$ and $R_{L}$ are $200\: \Omega$ and $1\:k\Omega,$ respectively. What is the range of $V_{i}$ that will maintain the Zener diode in the on' ... $34\: V$ $24\: V$ to $36\: V$ $18\: V$ to $24\: V$ $20\: V$ to $28\: V$

In the circuit shown, the breakdown voltage and the maximum current of the Zener diode are $20\:V$ and $60\:mA$, respectively. The values of $R_{1}$ and $R_{L}$ are $200\...

Arjun

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14

GATE ECE 2019 | Question: 35
The quantum efficiency $(\eta)$ and responsivity $(R)$ at wavelength $\lambda \:(\text{in}\: \mu m)$ in a p-i-n photodetector are related by $R= \frac{\eta \times \lambda}{1.24}$ $R= \frac{\lambda}{\eta \times 1.24}$ $R= \frac{1.24 \times\lambda}{\eta}$ $R= \frac{1.24}{\eta \times \lambda}$

The quantum efficiency $(\eta)$ and responsivity $(R)$ at wavelength $\lambda \:(\text{in}\: \mu m)$ in a p-i-n photodetector are related by$R= \frac{\eta \times \lambda}...

Arjun

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15

GATE ECE 2019 | Question: 50
Consider a long-channel MOSFET with a channel length $1\:\mu m$ and width $10\: \mu m.$ The device parameters are acceptor concentration $N_{A}=5 \times 10^{16}\: cm^{-3},$ electron mobility $\mu_{n}=800\: cm^{2}/V-s,$ ... _______ $mA$ (rounded off to two decimal places.). $[\varepsilon_{0}=8.854 \times 10^{-14}F/cm, \varepsilon_{si} =11.9]$

Consider a long-channel MOSFET with a channel length $1\:\mu m$ and width $10\: \mu m.$ The device parameters are acceptor concentration $N_{A}=5 \times 10^{16}\: cm^{-3}...

Arjun

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16

GATE ECE 2019 | Question: 36
Two identical copper wires $W1$ and $W2$ placed in parallel as shown in the figure, carry currents $I$ and $2I$, respectively, in opposite directions. If the two wires are separated by a distance of $4r$, then the magnitude of the magnetic field $\overrightarrow{B}$ between the wires at a ... $\frac{5\mu_{0}I}{6\pi r}$ $\frac{\mu_{0}^{2}I^{2}}{2\pi r^{2}}$

Two identical copper wires $W1$ and $W2$ placed in parallel as shown in the figure, carry currents $I$ and $2I$, respectively, in opposite directions. If the two wires ar...

Arjun

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17

GATE ECE 2019 | Question: 53
A CMOS inverter, designed to have a mid-point voltage $V_{1}$ equal to half of $V_{dd}.$ as shown in the figure, has the following parameters: $V_{dd}=3V$ $\mu_{n} C_{ox}=100\: \mu A/V^{2}; V_{tn}=0.7\:V $ for $\text{nMOS}$ ... of $\left(\frac{W}{L}\right)_{n}$ to $\left(\frac{W}{L}\right)_{p}$ is equal to _______ (rounded off to $3$ decimal places).

A CMOS inverter, designed to have a mid-point voltage $V_{1}$ equal to half of $V_{dd}.$ as shown in the figure, has the following parameters:$V_{dd}=3V$$\mu_{n} C_{ox}=1...

Arjun

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18

GATE ECE 2019 | Question: 54
In the circuit shown, the threshold voltages of the $pMOS\:\: (|V_{tp}|)$ and $nMOS\:\: (V_{tn})$ transistors are both equal to $1\:V.$ All the transistors have the same output resistance $r_{ds}$ of $6\:M\Omega.$ The other ... area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is ______ (rounded off to $1$ decimal place).

In the circuit shown, the threshold voltages of the $pMOS\:\: (|V_{tp}|)$ and $nMOS\:\: (V_{tn})$ transistors are both equal to $1\:V.$ All the transistors have the same ...

Arjun

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19

GATE ECE 2016 Set 2 | Question: 39
The figure shows a half-wave rectifier with a $475 \: \mu F$ filter capacitor. The load draws a constant current $I_{o}= 1 \: A$ from the rectifier. The figure also shows the input voltage $V_{i}$, the output voltage $V_{C}$ and the peak-to-peak voltage ... an amplitude of $10 \: V$ and a period of $1 \: ms$. The value of the ripple $u$ (in volts) is _________

The figure shows a half-wave rectifier with a $475 \: \mu F$ filter capacitor. The load draws a constant current $I_{o}= 1 \: A$ from the rectifier. The figure also shows...