Recent questions tagged analog-circuits

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GATE ECE 2020 | Question: 18
In the circuit shown below, all the components are ideal. If $V_{i}$ is $+2\:V$, the current $I_{o}$ sourced by the op-amp is __________ $\text{mA}$.

asked Feb 13, 2020 in Analog Circuits by jothee (1.8k points) | 36 views

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GATE ECE 2020 | Question: 33
The base of an $\text{npn BJT T1}$ has a linear doping profile $N_{B}\left ( x \right )$ as shown below. The base of another $\text{npn BJT T2}$ has a uniform doping $N_{B}$ of $10^{17}cm^{-3}$. All other parameters are identical for both the ... $\text{T1}$. approximately $2.5$ times that of $\text{T1}$. approximately $0.7$ times that of $\text{T1}$.

asked Feb 13, 2020 in Analog Circuits by jothee (1.8k points) | 48 views

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GATE ECE 2020 | Question: 35
For the $\text{BJT}$ in the amplifier shown below, $V_{BE}=0.7V,\:kT/q=26\:mV$. Assume that $\text{BJT}$ output resistance $(r_{o})$ is very high and the base current is negligible. The capacitors are also assumed to be short circuited at signal frequencies. The ... The low frequency voltage gain $v_{o}/v_{i}$ of the amplifier is $-89.42$ $-128.21$ $-178.85$ $-256.42$

asked Feb 13, 2020 in Analog Circuits by jothee (1.8k points) | 27 views

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GATE ECE 2020 | Question: 44
In the voltage regulator shown below, $V_{1}$ is the unregulated imput at $15\:V$. Assume $V_{BE}=0.7\:V$ and the base current is negligible for both the $\text{BJTs}$. If the regulated output $V_{O}$ is $9\:V$, the value of $R_{2}$ is ___________$\Omega$

asked Feb 13, 2020 in Analog Circuits by jothee (1.8k points) | 18 views

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GATE ECE 2019 | Question: 40
In the circuits shown the threshold voltage of each $\text{nMOS}$ transistor is $0.6\:V.$ Ignoring the effect of channel length modulation and body bias. the values of $\text{Vout}1$ and $\text{Vout} 2,$ respectively, in volts, are $1.8$ and $1.2$ $2.4$ and $2.4$ $1.8$ and $2.4$ $2.4$ and $1.2$

asked Feb 12, 2019 in Analog Circuits by Arjun (4.4k points) | 51 views

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GATE ECE 2016 Set 3 | Question: 14
Consider the circuit shown in the figure. Assuming $V_{EE1} = V_{EE2} = 0.7$ volt, the value of the dc voltage $V_{C2}$(in volt) is _______

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 21 views

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GATE ECE 2016 Set 3 | Question: 15
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin $3$ is _______

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 28 views

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GATE ECE 2016 Set 3 | Question: 21
For a superheterodyne receiver, the intermediate frequency is $15\ MHz$ and the local oscillator frequency is $3.5\ GHz$. If the frequency of the received signal is greater than the local oscillator frequency, then the image frequency (in $MHz$) is _______

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 21 views

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GATE ECE 2016 Set 3 | Question: 37
The injected excess electron concentration profile in the base region of an $npn$ BJT, biased in the active region, is linear, as shown in the figure. If the area of the emitter-base junction is $0.001\:cm^2 ,\mu_n=800cm^2/(V-s)$ in the ... is _________ (Given: thermal voltage $V_T=26 \: mV$ at room temperature, electronic charge $ q=1.6\times10^{-19}C$)

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 50 views

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GATE ECE 2016 Set 3 | Question: 41
In the circuit shown in the figure , the channel length modulation of all transistors is non-zero $(\lambda\neq0)$. Also, all transistors operate in saturation and have negligible body effect .The ac small signal voltage gain ($V_o/V_{in}$ ... $-g_{m1}(r_{o1}\mid\mid \left (\frac{1}{gm3}\mid\mid r_{o3})\mid\mid r_{o2} \right )$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 17 views

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GATE ECE 2016 Set 2 | Question: 6
In the circuit shown below, $V_{s}$ is a constant voltage source and $I_{L}$ is a constant current load. The value of $I_{L}$ that maximizes the power absorbed by the constant current load is $\frac{V_{S}}{4R} \\$ $\frac{V_{S}}{2R} \\$ $\frac{V_{S}}{R} \\$ $\infty$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 16 views

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GATE ECE 2016 Set 2 | Question: 7
The switch has been in position $1$ for a long time and abruptly changes to position $2$ at $t = 0$. If time $t$ is in seconds, the capacitor voltage $V_{C}$ (in volts) for $t > 0$ is given by $4\left ( 1- \text{ exp }\left ( -t/0.5 \right ) \right )$ ... $4\left ( 1-\text{ exp }\left ( -t/0.6 \right ) \right )$ $10 -6 \text{ exp }\left ( -t/0.6 \right )$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 14 views

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GATE ECE 2016 Set 2 | Question: 11
The Ebers-Moll model of a $BJT$ is valid only in active mode only in active and saturation modes only in active and cut-off modes in active, saturation and cut-off modes

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 11 views

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GATE ECE 2016 Set 2 | Question: 12
A long-channel $NMOS$ transistor is biased in the linear region with $V_{DS}=50$ $m$ $V$ and is used as a resistance. Which one of the following statement is $NOT$ correct? If the device width $W$ is increased, the resistance ... decreases. If the device length $L$ is increased, the resistance increases. If $V_{GS}$ is incresed, the resistance increases.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 23 views

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GATE ECE 2016 Set 2 | Question: 15
Which one of the following statements is correct about an ac-coupled common-emitter amplifier operating in the mid-band region? The device parasitic capacitances behave like open circuits, whereas coupling and bypass capacitances ... The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances behave like open circuits.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 18 views

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GATE ECE 2016 Set 2 | Question: 38
Consider a long-channel $NMOS$ transistor with source and body connected together. Assume that the electron mobility is independent of $V_{GS}$ and $V_{DS}.$ ... $and$ $g_{d}=\frac{\partial I_{D}}{\partial V_{DS}}$ The threshold voltage (in volts) of the transistor is _________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 86 views

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GATE ECE 2016 Set 2 | Question: 41
An opamp has a finite open loop voltage gain of $100$. Its input offset voltage $V_{ios}(=+5mV)$ is modeled as shown in the circuit below. The amplifier is ideal in all other respects. $V_{\text{input}}$ is $25 \: mV$. The output voltage (in millivolts) is _________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 11 views

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GATE ECE 2016 Set 2 | Question: 45
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s^{2}+2s \right )}$. The step response of the closed-loop system should have minimum settling time and have no overshoot. The required value of gain $k$ to achieve this is __________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 9 views

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GATE ECE 2016 Set 2 | Question: 46
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}.$ The positive value of $k$ for which the gain margin of the loop is exactly $0$ dB and the phase margin of the loop is exactly zero degree is _________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 30 views

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GATE ECE 2016 Set 1 | Question: 14
The following signal $V_i$ of peak voltage $8 \: V$ is applied to the non-inverting terminal of an ideal Op-amp.The transistor has $V_{EE}=0.7 \: V$, $\beta=100; \: V_{LED}=1.5 \: V$, $V_{CC}=10 \: V$ and $ – V_{CC}= – 10 \:V$. The number of times the LED glows is ________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 22 views

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GATE ECE 2016 Set 1 | Question: 15
Consider the oscillator circuit shown in the figure. The function of the network (shown in dotted lines) consisting of the $100 \: k \Omega$ resistor in series with the two diodes connected back-to-back is to: introduce amplitude ... circuit to oscillate at a single frequency. enable the loop gain to take on a value that produces square wave oscillations.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 16 views

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GATE ECE 2016 Set 1 | Question: 16
The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-$N$ counter (comprising $\div 2, \div 4, \div 8, \div 16$ outputs) is sketched below. The synthesizer is excited with a $5$ kHz signal (Input $1$). The free-running frequency ... $160 \: kHz, 80 \: kHz, 40 \: kHz, 20 \: kHz$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 16 views

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23

GATE ECE 2016 Set 1 | Question: 17
The output of the combinational circuit given below is $A+B+C$ $A(B+C)$ $B(C+A)$ $C(A+B)$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 20 views

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GATE ECE 2016 Set 1 | Question: 18
What is the voltage $V_{out}$ in the following circuit ? $0 V$ ($\mid V_T$ of PMOS$\mid$ + $V_T$ of NMOS)$/2$ Switching threshold of inverter $V_{DD}$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 19 views

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GATE ECE 2016 Set 1 | Question: 22
A superheterodyne receiver operates in the frequency range of $58$ MHz – $68$ MHz. The intermediate frequency $f_{IF}$ and local oscillator frequency $f_{LO}$ are chosen such that $f_{IF} \leq f_{LO}$. It is required that the image frequencies fall outside the $58$ MHz – $68$ MHz band. The minimum required $f_{IF}$ (in MHz) is _________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 18 views

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GATE ECE 2016 Set 1 | Question: 31
A network consisting of a finite number of linear resistor (R), inductor (L), and capacitor (C) elements, connected all in series or all in parallel, is excited with a source of the form ... $\sum_{k=1}^{3} a_k\cos(k\omega_0t+\phi_k) \\$ $\sum_{k=1}^{2} a_k\cos(k\omega_0t+\phi_k)$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 23 views

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GATE ECE 2016 Set 1 | Question: 33
An AC voltage source $V = 10 \sin(t)$ volts is applied to the following network. Assume that $R_1 = 3 k\Omega$, $R_2 = 6 k\Omega$ and $R_3 = 9k\Omega$, and that the diode is ideal. RMS current $I_{rms}$(in mA) through the diode is _______

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 17 views

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GATE ECE 2016 Set 1 | Question: 34
In the circuit shown in the figure, the maximum power (in watt) delivered to the resistor $R$ is _______

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 31 views

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29

GATE ECE 2016 Set 1 | Question: 40
An ideal opamp has voltage sources $V_1, V_3, V_5, \dots, V_{N-1}$ connected to the non-inverting input and $V_2, V_4, V_6, \dots, V_N$ connected to the inverting input as shown in the figure below $(+V_{CC}= 15$ volt, $ - V_{CC} = - 15$ volt ... $N$ approaches infinity, the output voltage (in volt) is _________

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 9 views

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30

GATE ECE 2015 Set 3 | Question: 9
In the circuit shown, the voltage $V_{X}$ (in Volts) is ________.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 12 views

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31

GATE ECE 2015 Set 3 | Question: 8
At very high frequencies, the peak output voltage $V_{0}$ (in Volts) is _______.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 12 views

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32

GATE ECE 2015 Set 3 | Question: 9
Which one of the following processes is preferred to form the gate dielectric $(SiO_{2})$ of MOSFETs ? Sputtering Molecular beam epitaxy Wet oxidation Dry oxidation

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 22 views

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33

GATE ECE 2015 Set 3 | Question: 10
If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TRUE? Current gain will increase Unity gain frequency will increase Emitter-base junction capacitance will increase Early Voltage will increase

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 17 views

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34

GATE ECE 2015 Set 3 | Question: 11
In the circuit shown in the figure, the BJT has a current gain $(\beta)$ of $50.$ For an emitter-base voltage ܸ $V_{EB} = 600\: mV,$ the emitter-collector voltage $V_{EC}$ (in Volts) is _______.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 8 views

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35

GATE ECE 2015 Set 3 | Question: 12
In the circuit shown using an ideal opamp, the $3$-dB cut-off frequency (in Hz) is _______.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 18 views

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36

GATE ECE 2015 Set 3 | Question: 13
In the circuit shown, assume that diodes $D_{1}$ and $D_{2}$ are ideal. In the steady state condition, the average voltage $V_{ab}$ (in Volts) across the $0.5\: \mu F$ capacitor is ______.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 14 views

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37

GATE ECE 2015 Set 3 | Question: 18
Consider a four-point moving average filter defined by the equation $y[n] = \displaystyle{}\sum _{i=0}^{3}\alpha_{i}\:x[n-i].$ ... $\alpha_{1} = \alpha_{2} = 0;\:\alpha_{0} = \alpha_{3}$

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 20 views

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GATE ECE 2015 Set 3 | Question: 34
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be $1\: mA$ at a drain-source voltage of $5\: V.$ When the drain-source voltage was increased to $6\: V$ while keeping gate-source voltage same, the ... the applied drain-source voltage. The channel length modulation parameter $\lambda\:(\text{in}\: V^{-1})$ is _______.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 16 views

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39

GATE ECE 2015 Set 3 | Question: 35
An npn BJT having reverse saturation current $I_{S} = 10^{-15}\:A$ is biased in the forward active region with $V_{BE} = 700\: mV.$ The thermal voltage $(V_{T})$ is $25\: mV$ and the current gain $(β)$ may vary from $50$ to $150$ due to manufacturing variations. The maximum emitter current $(\text{in}\: \mu A)$ is ________.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 25 views

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40

GATE ECE 2015 Set 3 | Question: 41
In the circuit shown, assume that the diodes $D1$ and $D2$ are ideal. The average value of voltage $V_{ab}\: (\text{in Volts}),$ across terminals $‘a’$ and $‘b’$ is _________.

asked Mar 28, 2018 in Analog Circuits by Milicevic3306 (15.8k points) | 10 views