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GATE2020EC: 18
In the circuit shown below, all the components are ideal. If $V_{i}$ is $+2\:V$, the current $I_{o}$ sourced by the opamp is __________ $\text{mA}$.
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GATE2020EC: 44
In the voltage regulator shown below, $V_{1}$ is the unregulated imput at $15\:V$. Assume $V_{BE}=0.7\:V$ and the base current is negligible for both the $\text{BJTs}$. If the regulated output $V_{O}$ is $9\:V$, the value of $R_{2}$ is ___________$\Omega$
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GATE2016314
Consider the circuit shown in the figure. Assuming $V_{EE1} = V_{EE2} = 0.7$ volt, the value of the dc voltage $V_{C2}$(in volt) is _______
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Mar 28, 2018
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gate2016ec3
numericalanswers
analogcircuits
voltagereferencecircuits
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4
GATE2016315
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin $3$ is _______
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Mar 28, 2018
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5
GATE2016321
For a superheterodyne receiver, the intermediate frequency is $15\ MHz$ and the local oscillator frequency is $3.5\ GHz$. If the frequency of the received signal is greater than the local oscillator frequency, then the image frequency (in $MHz$) is _______
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Mar 28, 2018
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gate2016ec3
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6
GATE2016211
The EbersMoll model of a $BJT$ is valid only in active mode only in active and saturation modes only in active and cutoff modes in active, saturation and cutoff modes
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Mar 28, 2018
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gate2016ec2
electronicdevices
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bjt
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7
GATE2016212
A longchannel $NMOS$ transistor is biased in the linear region with $V_{DS}=50$ $m$ $V$ and is used as a resistance. Which one of the following statement is $NOT$ correct? If the device width $W$ is increased, the resistance decreases. If ... the resistance decreases. If the device length $L$ is increased, the resistance increases. If $V_{GS}$ is incresed, the resistance increases.
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gate2016ec2
electronicdevices
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nmostransistor
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8
GATE2016241
An opamp has a finite open loop voltage gain of $100$. Its input offset voltage $V_{ios}(=+5mV)$ is modeled as shown in the circuit below. The amplifier is ideal in all other respects. $V_{\text{input}}$ is $25 \: mV$. The output voltage (in millivolts) is _________
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Mar 28, 2018
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gate2016ec2
numericalanswers
analogcircuits
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9
GATE2016245
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s^{2}+2s \right )}$. The step response of the closedloop system should have minimum settling time and have no overshoot. The required value of gain $k$ to achieve this is __________
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gate2016ec2
numericalanswers
analogcircuits
feedback
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10
GATE2016246
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}.$ The positive value of $k$ for which the gain margin of the loop is exactly $0$ dB and the phase margin of the loop is exactly zero degree is _________
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Mar 28, 2018
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gate2016ec2
numericalanswers
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11
GATE2016114
The following signal $V_i$ of peak voltage $8 \: V$ is applied to the noninverting terminal of an ideal Opamp.The transistor has $V_{EE}=0.7 \: V$, $\beta=100; \: V_{LED}=1.5 \: V$, $V_{CC}=10 \: V$ and $ – V_{CC}= – 10 \:V$. The number of times the LED glows is ________
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Mar 28, 2018
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gate2016ec1
numericalanswers
analogcircuits
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12
GATE2016115
Consider the oscillator circuit shown in the figure. The function of the network (shown in dotted lines) consisting of the $100 \: k \Omega$ resistor in series with the two diodes connected backtoback is to: introduce amplitude stabilization by ... the circuit to oscillate at a single frequency. enable the loop gain to take on a value that produces square wave oscillations.
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gate2016ec1
analogcircuits
oscillators
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13
GATE2016116
The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divideby$N$ counter (comprising $\div 2, \div 4, \div 8, \div 16$ outputs) is sketched below. The synthesizer is excited with a $5$ kHz signal (Input $1$). The freerunning frequency of the PLL is set ... $80 kHz, 40 \: kHz, \: 20 kHz, \: 10 kHz$ $160 \: kHz, 80 \: kHz, 40 \: kHz, 20 \: kHz$
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Mar 28, 2018
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gate2016ec1
analogcircuits
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14
GATE2016117
The output of the combinational circuit given below is $A+B+C$ $A(B+C)$ $B(C+A)$ $C(A+B)$
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Mar 28, 2018
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gate2016ec1
analogcircuits
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15
GATE2016118
What is the voltage $V_{out}$ in the following circuit ? $0 V$ ($\mid V_T$ of PMOS$\mid$ + $V_T$ of NMOS)$/2$ Switching threshold of inverter $V_{DD}$
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Mar 28, 2018
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gate2016ec1
analogcircuits
pmos
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16
GATE2016122
A superheterodyne receiver operates in the frequency range of $58$ MHz – $68$ MHz. The intermediate frequency $f_{IF}$ and local oscillator frequency $f_{LO}$ are chosen such that $f_{IF} \leq f_{LO}$. It is required that the image frequencies fall outside the $58$ MHz – $68$ MHz band. The minimum required $f_{IF}$ (in MHz) is _________
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gate2016ec1
numericalanswers
analogcircuits
oscillators
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17
GATE2016140
An ideal opamp has voltage sources $V_1, V_3, V_5, \dots, V_{N1}$ connected to the noninverting input and $V_2, V_4, V_6, \dots, V_N$ connected to the inverting input as shown in the figure below $(+V_{CC}= 15$ volt, $  V_{CC} =  15$ ... $N$ approaches infinity, the output voltage (in volt) is _________
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18
GATE201539
In the circuit shown, the voltage $V_{X}$ (in Volts) is ________.
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Mar 28, 2018
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gate2015ec3
analogcircuits
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19
GATE201538
At very high frequencies, the peak output voltage $V_{0}$ (in Volts) is _______.
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Mar 28, 2018
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gate2015ec3
numericalanswers
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20
GATE201539
Which one of the following processes is preferred to form the gate dielectric $(SiO_{2})$ of MOSFETs ? Sputtering Molecular beam epitaxy Wet oxidation Dry oxidation
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Mar 28, 2018
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gate2015ec3
analogcircuits
mosfet
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21
GATE2015310
If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TRUE? Current gain will increase Unity gain frequency will increase Emitterbase junction capacitance will increase Early Voltage will increase
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Mar 28, 2018
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Milicevic3306
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gate2015ec3
analogcircuits
transistors
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0
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22
GATE2015311
In the circuit shown in the figure, the BJT has a current gain $(\beta)$ of $50.$ For an emitterbase voltage ܸ $V_{EB} = 600\: mV,$ the emittercollector voltage $V_{EC}$ (in Volts) is _______.
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Mar 28, 2018
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gate2015ec3
numericalanswers
analogcircuits
bjt
0
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23
GATE2015312
In the circuit shown using an ideal opamp, the $3$dB cutoff frequency (in Hz) is _______.
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Mar 28, 2018
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gate2015ec3
numericalanswers
analogcircuits
opamps
0
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0
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24
GATE2015313
In the circuit shown, assume that diodes $D_{1}$ and $D_{2}$ are ideal. In the steady state condition, the average voltage $V_{ab}$ (in Volts) across the $0.5\: \mu F$ capacitor is ______.
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Mar 28, 2018
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gate2015ec3
numericalanswers
analogcircuits
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25
GATE2015318
Consider a fourpoint moving average filter defined by the equation $y[n] = \displaystyle{}\sum _{i=0}^{3}\alpha_{i}\:x[ni].$ The condition on the filter coefficients that results in a null at zero frequency is $\alpha_{1} = \alpha_{2} = 0;\:\alpha_{0} = \alpha_{3}$ ... $\alpha_{1} = \alpha_{2} = 0;\:\alpha_{0} = \alpha_{3}$
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Mar 28, 2018
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gate2015ec3
analogcircuits
filters
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26
GATE2015335
An npn BJT having reverse saturation current $I_{S} = 10^{15}\:A$ is biased in the forward active region with $V_{BE} = 700\: mV.$ The thermal voltage $(V_{T})$ is $25\: mV$ and the current gain $(β)$ may vary from $50$ to $150$ due to manufacturing variations. The maximum emitter current $(\text{in}\: \mu A)$ is ________.
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gate2015ec3
numericalanswers
electronicdevices
bjt
analogcircuits
0
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0
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27
GATE2015339
In the circuit shown, assume that the opamp is ideal. If the gain $(v_{0} / v_{in})$ is $–12,$ the value of $R\: (\text{in}\: k\Omega)$ is _____.
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gate2015ec3
analogcircuits
opamp
+1
vote
0
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28
GATE2015340
In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics:$k_{n} ݇ = \mu _{n}C_{ox}(W/L) = 1\:mA/V^{2};V_{TN} = 1V.$ Assume that the channel length modulation parameter $\lambda$ is zero and body is ... The minimum supply voltage ܸ$V_{DD}$ (in volts) needed to ensure that transistor $M_{1}$ operates in saturation mode of operation is _______.
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gate2015ec3
numericalanswers
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nmos
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29
GATE2015341
In the circuit shown, assume that the diodes $D1$ and $D2$ are ideal. The average value of voltage $V_{ab}\: (\text{in Volts}),$ across terminals $‘a’$ and $‘b’$ is _________.
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gate2015ec3
numericalanswers
analogcircuits
diodes
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30
GATE2015211
If the circuit shown has to function as a clamping circuit, then which one of the following conditions should be satisfied for the sinusoidal signal of period $T?$ $RC \ll T$ $RC = 0.35\: T$ $RC \approx T$ $RC \gg T$
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gate2015ec2
analogcircuits
clampingcircuits
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31
GATE2015212
In the circuit shown, $V_{0} = V_{0A}$ for switch $SW$ in position $A$ and $V_{0} = V_{0B}$ for $SW$ in position $B$. Assume that the opamp is ideal. The value of $\dfrac{V_{0B}}{V_{0A}}$ is ___________.
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gate2015ec2
numericalanswers
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32
GATE2015213
In the bistable circuit shown, the ideal opamp has saturation levels of $\pm\: 5\: V.$ The value of $R_{1} \text{(in}\: k\Omega)$ that gives a hysteresis width of $500\: mV$ is ________.
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opamp
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33
GATE2015230
An $LC$ tank circuit consists of an ideal capacitor $C$ connected in parallel with a coil of inductance $L$ having an internal resistance $R.$ The resonant frequency of the tank circuit is $\dfrac{1}{2\pi \sqrt{LC}}$ $\dfrac{1}{2\pi \sqrt{LC}}\sqrt{1R^{2}\dfrac{C}{L}}$ $\dfrac{1}{2\pi \sqrt{LC}}\sqrt{1 \dfrac{L}{R^{2}C}}$ $\dfrac{1}{2\pi \sqrt{LC}}\left(1R^{2}\dfrac{C}{L}\right)$
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gate2015ec2
analogcircuits
tankcircuits
differentialequations
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34
GATE2015240
Assuming that the opamp in the circuit shown below is ideal, the output voltage ܸ$V_{o}$ (in volts) is________.
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analogcircuits
opamps
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35
GATE2015241
For the voltage regulator circuit shown, the input voltage $(V_{in})$ is $20 V \pm 20\%$ and the regulated output voltage $(V_{out})$ is $10\: V.$ Assume the opamp to be ideal. For a load $R_L$ drawing $200\: mA,$ the maximum power dissipation in $Q_{1}\:\text{(in Watts)}$ is ________.
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numericalanswers
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0
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36
GATE2015242
In the ac equivalent circuit shown, the two BJTs are biased in active region and have identical parameters with $\beta \gg 1$. The open circuit small signal voltage gain is approximately _______.
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bjt
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37
GATE2015134
A MOSFET in saturation has a drain current of $1$ mA for $V_{DS} =0.5 \: V$. If the channel length modulation coefficient is $0.05 \: V^{1}$, the output resistance (in $k \Omega$) of the MOSFET is ___________.
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gate2015ec1
numericalanswers
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38
GATE2015139
For the NMOSFET in the circuit shown, the threshold voltage is $V_{th}$, where $V_{th}>0$. The source voltage $V_{SS}$ is varied from $0$ to $V_{DD}$. Neglecting the channel length modulation, the drain current $I_D$ as a function of $V_{SS}$ is represented by
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gate2015ec1
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39
GATE2015140
In the circuit shown, assume that the opamp is ideal. The bridge output voltage $V_0$ (in mV) for $\delta=0.05$ is __________
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gate2015ec1
numericalanswers
analogcircuits
opamp
0
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0
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40
GATE2015141
The circuit shown in the figure has an ideal opamp. The oscillation frequency and the condition to sustain the oscillations, respectively, are $\frac{1}{CR}$ and $R_1=R_2 \\ $ $\frac{1}{CR}$ and $R_1=4R_2 \\ $ $\frac{1}{2CR}$ and $R_1=R_2 \\ $ $\frac{1}{2CR}$ and $R_1=4R_2 $
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