Recent questions tagged cmos / GO Electronics

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GATE ECE 2019 | Question: 13
A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin $NM_{L}$ and the HIGH noise margin $NM_{H}$? ... . $NM_{L}$ decreases and $NM_{H}$ increases. Both $NM_{L}$ and $NM_{H}$ increases. No change in the noise margins.

A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would ...

Arjun

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Arjun asked Feb 12, 2019

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GATE ECE 2019 | Question: 53
A CMOS inverter, designed to have a mid-point voltage $V_{1}$ equal to half of $V_{dd}.$ as shown in the figure, has the following parameters: $V_{dd}=3V$ $\mu_{n} C_{ox}=100\: \mu A/V^{2}; V_{tn}=0.7\:V $ for $\text{nMOS}$ ... of $\left(\frac{W}{L}\right)_{n}$ to $\left(\frac{W}{L}\right)_{p}$ is equal to _______ (rounded off to $3$ decimal places).

A CMOS inverter, designed to have a mid-point voltage $V_{1}$ equal to half of $V_{dd}.$ as shown in the figure, has the following parameters:$V_{dd}=3V$$\mu_{n} C_{ox}=1...

Arjun

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Arjun asked Feb 12, 2019

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GATE ECE 2016 Set 2 | Question: 16
Transistor geometries in a $CMOS$ inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor $C$. This design is to be converted to that of a $NOR$ circuit in the same ... should not be changed. Widths of $PMOS$ transistors should be unchanged, while widths of $NMOS$ transistors should be halved.

Transistor geometries in a $CMOS$ inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor $C$. This des...

Milicevic3306

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Milicevic3306 asked Mar 27, 2018

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GATE ECE 2014 Set 2 | Question: 10
In CMOS technology, shallow P-well or N-well regions can be formed using low pressure chemical vapour deposition low energy sputtering low temperature dry oxidation low energy ion-implantation

In CMOS technology, shallow P-well or N-well regions can be formed usinglow pressure chemical vapour deposition low energy sputteringlow temperature dry oxidationlow ener...

Milicevic3306

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Milicevic3306 asked Mar 26, 2018

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GATE ECE 2012 | Question: 37
In the CMOS circuit shown, electron and hole mobilities are equal, and $M1$ and $M2$ are equally sized. The device $M1$ is in the linear region if $V_{in}\lt 1.875\:V$ $1.875\:V\lt V_{in}\lt 3.125\:V$ $V_{in}\gt 3.125\:V$ $0\lt V_{in}\lt 5\:V$

In the CMOS circuit shown, electron and hole mobilities are equal, and $M1$ and $M2$ are equally sized. The device $M1$ is in the linear region if$V_{in}\lt 1.875\:V$$1.8...

Milicevic3306

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Milicevic3306 asked Mar 25, 2018