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Recent questions tagged digital-circuits

1 votes
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44
GATE ECE 2015 Set 2 | Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively,NOR, OROR, NANDNAND, ORAND,NA...
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45
GATE ECE 2015 Set 2 | Question: 15
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator? MOV B, M PCHL RNZ SBI BEH
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator?MOV B, MPCHLRNZSBI BEH
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46
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
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47
GATE ECE 2015 Set 2 | Question: 36
A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$ Which one of the product of sums given below is equal to the function $F(X, Y, Z)?$ ...
A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $$F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$$Which one of the product of sums given bel...
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48
GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-...
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50
GATE ECE 2015 Set 1 | Question: 14
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively B and F A and F H and F A and C
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectivelyB and FA and FH and FA and C
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51
GATE ECE 2015 Set 1 | Question: 15
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ___________
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of addr...
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52
GATE ECE 2015 Set 1 | Question: 16
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog value (in Volts) corresponding to the digital signal $1111$ is _________
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog ...
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53
GATE ECE 2015 Set 1 | Question: 36
The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ ... $(X+\overline{Y}+\overline{Z})(\overline{X}+Y+Z)(\overline{X}+\overline{Y}+Z)(X + Y + Z)$
The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ converted into the canonica...
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56
GATE ECE 2014 Set 4 | Question: 15
In the circuit shown in the figure, if $C=0$, the expression for $Y$ is $Y=A \overline{B} + \overline{A}B$ $Y=A+B$ $Y=\overline{A} + \overline{B}$ $Y=A \: B$
In the circuit shown in the figure, if $C=0$, the expression for $Y$ is$Y=A \overline{B} + \overline{A}B$$Y=A+B$$Y=\overline{A} + \overline{B}$$Y=A \: B$
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57
GATE ECE 2014 Set 4 | Question: 16
The output $(Y)$ of the circuit shown in the figure is $\overline{A} + \overline{B} +C$ $A + \overline{B} \cdot \overline{C} + A \cdot \overline{C}$ $\overline{A} +B+\overline{C}$ $A \cdot B \cdot \overline{C}$
The output $(Y)$ of the circuit shown in the figure is$\overline{A} + \overline{B} +C$$A + \overline{B} \cdot \overline{C} + A \cdot \overline{C}$$\overline{A} +B+\overli...
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60
GATE ECE 2014 Set 4 | Question: 42
An $8085$ microprocessor executes $ STA 1234H $ with starting address location $1FFEH$ (STA copies the contents of the Accumulator to the $16$ ... $1FH, FEH, 1FH, FFH, 12H$ $1FH, 1FH, 12H, 12H$ $1FH, 1FH, 12H, 20H, 12H$
An $8085$ microprocessor executes $“STA 1234H”$ with starting address location $1FFEH$ (STA copies the contents of the Accumulator to the $16$- bit address location)....
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61
GATE ECE 2014 Set 3 | Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch Master-Slave D Flip Flop
The circuit shown in the figure is a Toggle Flip FlopJK Flip FlopSR LatchMaster-Slave D Flip Flop
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63
GATE ECE 2014 Set 3 | Question: 40
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
1 votes
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65
GATE ECE 2014 Set 3 | Question: 42
If $X$ and $Y$ are inputs and the Difference $(D=X-Y)$ and the Borrow $(B)$ are the outputs, which one of the following diagrams implements a half-subtractor?
If $X$ and $Y$ are inputs and the Difference $(D=X-Y)$ and the Borrow $(B)$ are the outputs, which one of the following diagrams implements a half-subtractor?
0 votes
1 answer
67
GATE ECE 2014 Set 2 | Question: 14
For an $n$-variable Boolean function, the maximum number of prime implicants is $2(n-1)$ $n/2$ $2^{n}$ $2^{n-1}$
For an $n$-variable Boolean function, the maximum number of prime implicants is$2(n-1)$$n/2$$2^{n}$$2^{n-1}$
1 votes
1 answer
68
GATE ECE 2014 Set 2 | Question: 15
The number of bytes required to represent the decimal number $1856357$ in packed BCD (Binary Coded Decimal) form is ___________.
The number of bytes required to represent the decimal number $1856357$ in packed BCD (Binary Coded Decimal) form is ___________.
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70
GATE ECE 2014 Set 2 | Question: 17
As FIR system is described by the system function $ H(z) = 1 + \frac{7}{2} z^{-1} + \frac{3}{2}z^{-2}$. The system is maximum phase minimum phase mixed phase zero phase
As FIR system is described by the system function $$ H(z) = 1 + \frac{7}{2} z^{-1} + \frac{3}{2}z^{-2}$$. The system ismaximum phaseminimum phasemixed phasezero phase
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71
GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots...
1 votes
2 answers
73
GATE ECE 2014 Set 1 | Question: 15
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to $X$ $Y$ $XY$ $X+Y$
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to$X$$Y$$XY$$X+Y$
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74
GATE ECE 2014 Set 1 | Question: 16
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.
Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of th...
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78
GATE ECE 2013 | Question: 45
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ ... $0500H-08FFH, 1500H-18FFH, 3500H-38FFH, 5500H-58FFH$ $0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH$
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ respectively are mapp...
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