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Recent questions tagged diodes
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GATE ECE 2016 Set 3  Question: 13
The diodes $D1$ and $D2$ in the figure are ideal and the capacitors are identical. The product $RC$ is very large compared to the time period of the ac voltage. Assuming that the diodes do not breakdown in the reverse bias, the output voltage $V_o$(in volt) at the steady state is _______
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Mar 28, 2018
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Network Solution Methods
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gate2016ec3
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2
GATE ECE 2016 Set 2  Question: 34
The switch $S$ in the circuit shown has been closed for a long time. It is opened at $t = 0$ and remains open after that. Assume that the diode has zero reverse current and zero forward voltage drop. The steady state magnitude of the capacitor voltage $V_{c}$ (in volts) is ______
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Mar 28, 2018
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Network Solution Methods
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3
GATE ECE 2015 Set 3  Question: 41
In the circuit shown, assume that the diodes $D1$ and $D2$ are ideal. The average value of voltage $V_{ab}\: (\text{in Volts}),$ across terminals $‘a’$ and $‘b’$ is _________.
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Mar 28, 2018
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Analog Circuits
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Milicevic3306
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12
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gate2015ec3
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4
GATE ECE 2015 Set 2  Question: 39
The diode in the circuit given below has $V_{ON} = 0.7\:V$ but is ideal otherwise. The current $(\text{in}\: mA)$ in the $4\: k\Omega$ resistor is _______.
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Mar 28, 2018
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Analog Circuits
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15
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gate2015ec2
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5
GATE ECE 2015 Set 1  Question: 11
For the circuit with ideal diodes shown in the figure, the shape of the output $v_{\text{out}}$ for the given sine wave input $v_{\text{in}}$ will be
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Mar 28, 2018
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Analog Circuits
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Milicevic3306
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19
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gate2015ec1
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6
GATE ECE 2015 Set 1  Question: 46
The openloop transfer function of a plant in a unity feedback configuration is given as $G(s) = \frac{K(s+4)}{(s+8)(s^29)}$. The value of the gain $K(>0)$ for which $1+j2$ lies on the root locus is _________.
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Mar 28, 2018
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Network Solution Methods
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14
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gate2015ec1
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7
GATE ECE 2014 Set 3  Question: 13
The figure shows a halfwave rectifier. The diode $D$ is ideal. The average steadystate current (in Amperes) through the diode is approximately ___________.
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Mar 26, 2018
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Analog Circuits
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Milicevic3306
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44
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gate2014ec3
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8
GATE ECE 2013  Question: 42
In the circuit shown below, $Q_{1}$ has negligible collectortoemitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is $+5 V, X$ and $Y$ are digital signals with $0\: V$ as logic $0$ and $V_{cc}$ as logic $1,$ then the Boolean expression for $Z$ is $XY$ $\overline{X}Y$ $X\overline{Y}$ $\overline{XY}$
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Mar 26, 2018
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Analog Circuits
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18
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gate2013ec
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9
GATE ECE 2013  Question: 43
A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is $\sin \omega t$ $(\sin \omega t \:+ \mid \sin \omega t \mid)/2$ $(\sin \omega t \:  \mid \sin \omega t \mid)/2$ $0$ for all $t$
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Mar 26, 2018
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Analog Circuits
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23
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gate2013ec
analogcircuits
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10
GATE ECE 2013  Question: 4
In a forward biased $pn$ junction diode, the sequence of events that best describes the mechanism of current flow is injection, and subsequent diffusion and recombination of minority carriers injection, and subsequent drift and ... , and subsequent diffusion and generation of minority carriers extraction, and subsequent drift and recombination of minority carriers
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Mar 26, 2018
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Analog Circuits
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18
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gate2013ec
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11
GATE ECE 2012  Question: 55
The transfer function of a compensator is given as $G_c(s)=\frac{s+a}{s+b}$ The phase of the above lead compensator is maximum at $\sqrt{2}$ rad/s $\sqrt{3}$ rad/s $\sqrt{6}$ rad/s $\frac{1}{\sqrt{3}}$ rad/s
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Mar 25, 2018
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Network Solution Methods
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21
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gate2012ec
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12
GATE ECE 2017 Set 2  Question: 12
The output $V_0$ of the diode circuit shown in the figure is connected to an averaging DC voltmeter. The reading on the DC voltmeter in Volts, neglecting the voltage drop across the diode, is _________________.
asked
Nov 23, 2017
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Analog Circuits
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admin
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