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Recent questions tagged gate2016-ec-2
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41
GATE ECE 2016 Set 2 | Question: 30
In the given circuit, each resistor has a value equal to $1\Omega$. What is the equivalent resistance across the terminals $a$ and $b$? $1/6 \: \Omega$ $1/3 \: \Omega$ $9/20 \: \Omega$ $8/15 \: \Omega$
In the given circuit, each resistor has a value equal to $1\Omega$. What is the equivalent resistance across the terminals $a$...
Milicevic3306
16.0k
points
86
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Milicevic3306
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Mar 27, 2018
Electronic Devices
gate2016-ec-2
electronic-devices
+
–
0
votes
0
answers
42
GATE ECE 2016 Set 2 | Question: 31
In the circuit shown in the figure, the magnitude of the current (in amperes) through $R_{2}$ is ____
In the circuit shown in the figure, the magnitude of the current (in amperes) through $R_{2}$ is ____
Milicevic3306
16.0k
points
85
views
Milicevic3306
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Mar 27, 2018
Electronic Devices
gate2016-ec-2
numerical-answers
electronic-devices
+
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0
votes
0
answers
43
GATE ECE 2016 Set 2 | Question: 32
A continuous-time filter with transfer function $H\left ( s \right )= \frac{2s+6}{s^{2}+6s+8}$ ... sampled at $2$ $Hz$, is identical at the sampling instants to the impulse response of the discrete time-filter. The value of $k$ is _________
A continuous-time filter with transfer function $H\left ( s \right )= \frac{2s+6}{s^{2}+6s+8}$ is converted to a discrete-time filter with transfer function $G\left ( z\r...
Milicevic3306
16.0k
points
133
views
Milicevic3306
asked
Mar 27, 2018
Network Solution Methods
gate2016-ec-2
numerical-answers
network-solution-methods
transfer-function
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0
votes
0
answers
44
GATE ECE 2016 Set 2 | Question: 34
The switch $S$ in the circuit shown has been closed for a long time. It is opened at $t = 0$ and remains open after that. Assume that the diode has zero reverse current and zero forward voltage drop. The steady state magnitude of the capacitor voltage $V_{c}$ (in volts) is ______
The switch $S$ in the circuit shown has been closed for a long time. It is opened at $t = 0$ and remains open after that. Assume that the diode has zero reverse current a...
Milicevic3306
16.0k
points
155
views
Milicevic3306
asked
Mar 27, 2018
Network Solution Methods
gate2016-ec-2
numerical-answers
network-solution-methods
diodes
steady-state
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–
0
votes
0
answers
45
GATE ECE 2016 Set 2 | Question: 35
A voltage $V_{G}$ is applied across a $MOS$ capacitor with metal gate and $p$-type silicon substrate at $T=300$ $K$. The inversion carrier density (in number of carriers per unit area) for $V_{G}= 0.8$ $V$ is $2\times 10^{11} cm^{-2}.$ For $V_{G}= 1.3$ $V$, the ... $6.0\times 10^{11}cm^{-2}$ $7.2\times 10^{11}cm^{-2}$ $8.4\times 10^{11}cm^{-2}$
A voltage $V_{G}$ is applied across a $MOS$ capacitor with metal gate and $p$-type silicon substrate at $T=300$ $K$. The inversion carrier density (in number of carriers ...
Milicevic3306
16.0k
points
79
views
Milicevic3306
asked
Mar 27, 2018
Electronic Devices
gate2016-ec-2
mos-capacitor
electronic-devices
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–
0
votes
0
answers
46
GATE ECE 2016 Set 2 | Question: 36
Consider avalanche breakdown in a silicon $p^{+}n$ junction. The $n$-region is uniformly doped with a donor density $N_{D}.$ ... $N_{D}\times {V_{BR}}= \text{constant}$ $N_{D}/{V_{BR}}= \text{constant}$
Consider avalanche breakdown in a silicon $p^{+}n$ junction. The $n$-region is uniformly doped with a donor density $N_{D}.$ Assume that breakdown occurs when the magnitu...
Milicevic3306
16.0k
points
169
views
Milicevic3306
asked
Mar 27, 2018
Electronic Devices
gate2016-ec-2
electronic-devices
p-n-junction
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0
votes
0
answers
47
GATE ECE 2016 Set 2 | Question: 37
Consider a region of silicon devoid of electrons and holes, with an ionized donor density of $N_{d}^{+}=10^{17} cm^{-3}.$ The electric field at $x = 0$ is $0\: V/cm$ and the electric field at $x=L$ is $50$ $kV/cm$ in the positive $x$ direction, ... $\epsilon _{r}=11.7$ for silicon, the value of $L$ in $nm$ is ___________
Consider a region of silicon devoid of electrons and holes, with an ionized donor density of $N_{d}^{+}=10^{17} cm^{-3}.$ The electric field at $x = 0$ is $0\: V/cm$ and ...
Milicevic3306
16.0k
points
162
views
Milicevic3306
asked
Mar 27, 2018
Electronic Devices
gate2016-ec-2
numerical-answers
electronic-devices
silicon
+
–
0
votes
0
answers
48
GATE ECE 2016 Set 2 | Question: 38
Consider a long-channel $NMOS$ transistor with source and body connected together. Assume that the electron mobility is independent of $V_{GS}$ and $V_{DS}.$ ... $and$ $g_{d}=\frac{\partial I_{D}}{\partial V_{DS}}$ The threshold voltage (in volts) of the transistor is _________
Consider a long-channel $NMOS$ transistor with source and body connected together. Assume that the electron mobility is independent of $V_{GS}$ and $V_{DS}.$ Given,$g_{m}...
Milicevic3306
16.0k
points
214
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
nmos-transistor
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–
0
votes
0
answers
49
GATE ECE 2016 Set 2 | Question: 39
The figure shows a half-wave rectifier with a $475 \: \mu F$ filter capacitor. The load draws a constant current $I_{o}= 1 \: A$ from the rectifier. The figure also shows the input voltage $V_{i}$, the output voltage $V_{C}$ and the peak-to-peak voltage ... an amplitude of $10 \: V$ and a period of $1 \: ms$. The value of the ripple $u$ (in volts) is _________
The figure shows a half-wave rectifier with a $475 \: \mu F$ filter capacitor. The load draws a constant current $I_{o}= 1 \: A$ from the rectifier. The figure also shows...
Milicevic3306
16.0k
points
302
views
Milicevic3306
asked
Mar 27, 2018
Electronic Devices
gate2016-ec-2
numerical-answers
electronic-devices
+
–
0
votes
0
answers
50
GATE ECE 2016 Set 2 | Question: 40
In the opamp circuit shown, the Zener diodes $Z1$ and $Z2$ clamp the output voltage $V_{0}$ to $+5V$ or $-5 V$. The switch $S$ is initially closed and is opened at time $t=0$. The time $t=t_{1}$ (in seconds) at which $V_{0}$ changes state is ________
In the opamp circuit shown, the Zener diodes $Z1$ and $Z2$ clamp the output voltage $V_{0}$ to $+5V$ or $-5 V$. The switch $S$ is initially closed and is opened at time $...
Milicevic3306
16.0k
points
117
views
Milicevic3306
asked
Mar 27, 2018
Electronic Devices
gate2016-ec-2
numerical-answers
electronic-devices
zener-diode
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–
0
votes
0
answers
51
GATE ECE 2016 Set 2 | Question: 41
An opamp has a finite open loop voltage gain of $100$. Its input offset voltage $V_{ios}(=+5mV)$ is modeled as shown in the circuit below. The amplifier is ideal in all other respects. $V_{\text{input}}$ is $25 \: mV$. The output voltage (in millivolts) is _________
An opamp has a finite open loop voltage gain of $100$. Its input offset voltage $V_{ios}(=+5mV)$ is modeled as shown in the circuit below. The amplifier is ideal in all o...
Milicevic3306
16.0k
points
119
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
op-amps
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–
0
votes
0
answers
52
GATE ECE 2016 Set 2 | Question: 42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the add...
Milicevic3306
16.0k
points
97
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-2
digital-circuits
microprocessor
rom
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–
0
votes
0
answers
53
GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digita...
Milicevic3306
16.0k
points
217
views
Milicevic3306
asked
Mar 27, 2018
Number Representations
gate2016-ec-2
digital-circuits
analog-to-digital-converter
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0
votes
0
answers
54
GATE ECE 2016 Set 2 | Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. ...
Milicevic3306
16.0k
points
348
views
Milicevic3306
asked
Mar 27, 2018
Digital Circuits
gate2016-ec-2
digital-circuits
state-transition-diagram
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–
0
votes
0
answers
55
GATE ECE 2016 Set 2 | Question: 45
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s^{2}+2s \right )}$. The step response of the closed-loop system should have minimum settling time and have no overshoot. The required value of gain $k$ to achieve this is __________
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s^{2}+2s \right )}$. The step response of the closed-loop system should have minimum settling tim...
Milicevic3306
16.0k
points
100
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
feedback
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–
0
votes
0
answers
56
GATE ECE 2016 Set 2 | Question: 46
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}.$ The positive value of $k$ for which the gain margin of the loop is exactly $0$ dB and the phase margin of the loop is exactly zero degree is _________
In the feedback system shown below $G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}.$ The positive v...
Milicevic3306
16.0k
points
120
views
Milicevic3306
asked
Mar 27, 2018
Analog Circuits
gate2016-ec-2
numerical-answers
analog-circuits
feedback
+
–
0
votes
0
answers
57
GATE ECE 2016 Set 2 | Question: 47
The asymptotic Bode phase plot of $G\left ( s \right )=\frac{k}{\left ( s+0.1 \right )\left ( s+10 \right )\left ( s+p_{1} \right )},$ with $k$ and $p_{1}$ both positive, is shown below. The value of $p_{1}$ is _______
The asymptotic Bode phase plot of $G\left ( s \right )=\frac{k}{\left ( s+0.1 \right )\left ( s+10 \right )\left ( s+p_{1} \right )},$ with $k$ and $p_{1}$ both positive,...
Milicevic3306
16.0k
points
102
views
Milicevic3306
asked
Mar 27, 2018
Control Systems
gate2016-ec-2
numerical-answers
control-systems
bode-and-root-locus-plots
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–
0
votes
0
answers
58
GATE ECE 2016 Set 2 | Question: 48
An information source generates a binary sequence $\left \{ \alpha _{n} \right \}$. $\alpha _{n}$ can take one of the two possible values $-1$ and $+1$ with equal probability and are statistically independent and identically distributed. This sequence is precoded ... there is a null at $f=\frac{1}{3T}$ in the power spectral density of $X(t)$, then $k$ is ________
An information source generates a binary sequence $\left \{ \alpha _{n} \right \}$. $\alpha _{n}$ can take one of the two possible values $-1$ and $+1$ with equal probabi...
Milicevic3306
16.0k
points
632
views
Milicevic3306
asked
Mar 27, 2018
Communications
gate2016-ec-2
numerical-answers
autocorrelation-and-power-spectral-density
communications
+
–
0
votes
0
answers
59
GATE ECE 2016 Set 2 | Question: 49
An ideal band-pass channel $500 \: Hz –2000 \:Hz$ is deployed for communication. A modem is designed to transmit bits at the rate of $4800$ bits/s using $16-QAM$. The roll-off factor of a pulse with a raised cosine spectrum that utilizes the entire frequency band is __________
An ideal band-pass channel $500 \: Hz –2000 \:Hz$ is deployed for communication. A modem is designed to transmit bits at the rate of $4800$ bits/s using $16-QAM$. The r...
Milicevic3306
16.0k
points
150
views
Milicevic3306
asked
Mar 27, 2018
Communications
gate2016-ec-2
numerical-answers
communications
+
–
0
votes
0
answers
60
GATE ECE 2016 Set 2 | Question: 50
Consider a random process $X\left ( t \right )=3V(t)-8,$ where $V(t)$ is a zero mean stationary random process with autocorrelation $R_{v}\left ( \tau \right )=4e^{-5\mid \tau \mid}.$ The power in $X(t)$ is _________
Consider a random process $X\left ( t \right )=3V(t)-8,$ where $V(t)$ is a zero mean stationary random process with autocorrelation $R_{v}\left ( \tau \right )=4e^{-5\mid...
Milicevic3306
16.0k
points
113
views
Milicevic3306
asked
Mar 27, 2018
Communications
gate2016-ec-2
numerical-answers
communications
autocorrelation-and-power-spectral-density
+
–
0
votes
0
answers
61
GATE ECE 2016 Set 2 | Question: 51
A binary communication system makes use of the symbols zero and one . There are channel errors. Consider the following events: ... in bits that you obtain when you learn which symbol has been received (while you know that a zero has been transmitted) is _________
A binary communication system makes use of the symbols “zero” and “one”. There are channel errors. Consider the following events:$\begin{array}{ll} x_{0}& : & \t...
Milicevic3306
16.0k
points
117
views
Milicevic3306
asked
Mar 27, 2018
Communications
gate2016-ec-2
numerical-answers
communications
+
–
0
votes
0
answers
62
GATE ECE 2016 Set 2 | Question: 52
The parallel-plate capacitor shown in the figure has movable plates. The capacitor is charged so that the energy stored in it is $E$ when the plate separation is $d$. The capacitor is then isolated electrically and the plate are moved such that the plate ... , what is the energy stored in the capacitor, neglecting fringing effects? $2E$ $\sqrt{2}E$ $E$ $E/2$
The parallel-plate capacitor shown in the figure has movable plates. The capacitor is charged so that the energy stored in it is $E$ when the plate separation is $d$. The...
Milicevic3306
16.0k
points
136
views
Milicevic3306
asked
Mar 27, 2018
Electronic Devices
gate2016-ec-2
electronic-devices
+
–
0
votes
0
answers
63
GATE ECE 2016 Set 2 | Question: 53
A lossless microstrip transmission line consists of a trace of width $w$. It is drawn over a pratically infinite ground plane and is separated by a dielectric slab of thickness $t$ and relative permittivity $\varepsilon _{r}> 1.$ The inductance per unit length and the ... $Z_{0}< \sqrt{\frac{Lt}{\varepsilon _{0}\varepsilon _{\gamma}t}}$
A lossless microstrip transmission line consists of a trace of width $w$. It is drawn over a pratically infinite ground plane and is separated by a dielectric slab of thi...
Milicevic3306
16.0k
points
150
views
Milicevic3306
asked
Mar 27, 2018
Electromagnetics
gate2016-ec-2
electromagnetics
+
–
0
votes
0
answers
64
GATE ECE 2016 Set 2 | Question: 54
A microwave circuit consisting of lossless transmission lines $T_{1}$ and $T_{2}$ is shown in the figure. The plot shows the magnitude of the input reflection coefficient $\Gamma$ as a function of frequency $f$. The phase velocity of the signal in the transmission lines is $2\times 10^{8}$ $m/s$. The length $L$ (in meters) of $T_{2}$ is _________
A microwave circuit consisting of lossless transmission lines $T_{1}$ and $T_{2}$ is shown in the figure. The plot shows the magnitude of the input reflection coefficient...
Milicevic3306
16.0k
points
104
views
Milicevic3306
asked
Mar 27, 2018
Electromagnetics
gate2016-ec-2
numerical-answers
electromagnetics
transmission-lines
+
–
0
votes
0
answers
65
GATE ECE 2016 Set 2 | Question: 55
A positive charge $q$ is placed at $x=0$ between two infinte metal plates placed at $x=-d$ and at $x=+d$ respectively. The metal plates lie in the $yz$ plane. The charge is at rest at $t=0$, when a voltage $+V$ is applied to the plate at $-d$ and ... that the charge $q$ takes to reach the right plate is proportional to $d/V$ $\sqrt{d}/V$ $d/\sqrt{V}$ $\sqrt{d/V}$
A positive charge $q$ is placed at $x=0$ between two infinte metal plates placed at $x=-d$ and at $x=+d$ respectively. The metal plates lie in the $yz$ plane. ...
Milicevic3306
16.0k
points
92
views
Milicevic3306
asked
Mar 27, 2018
Vector Analysis
gate2016-ec-2
vector-analysis
+
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