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Recent questions tagged sequential-circuit
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1
GATE ECE 2010 | Question: 37
Assuming that all flip-flops are in reset condition initially, the count sequence observed at $\text{Q}_\text{A}$ in the circuit shown is $0010111 \ldots$ $0001011 \ldots$ $0101111 \ldots$ $0110100 \ldots$
admin
asked
in
Sequential Circuits
Sep 15, 2022
by
admin
43.6k
points
10
views
gate2010-ec
digital-circuits
sequential-circuit
flip-flop
1
vote
0
answers
2
GATE ECE 2011 | Question: 41
Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarrow 11 \rightarrow 01 \rightarrow 10 \rightarrow 00 \rightarrow \cdots$ The connections to the ...
admin
asked
in
Sequential Circuits
Sep 3, 2022
by
admin
43.6k
points
8
views
gate2011-ec
digital-circuits
sequential-circuit
flip-flop
0
votes
0
answers
3
GATE ECE 2021 | Question: 46
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
Arjun
asked
in
Digital Circuits
Feb 20, 2021
by
Arjun
6.0k
points
150
views
gateec-2021
numerical-answers
digital-circuits
sequential-circuit
counters
1
vote
0
answers
4
GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
go_editor
asked
in
Number Representations
Feb 13, 2020
by
go_editor
1.9k
points
329
views
gate2020-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
5
GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
121
views
gate2016-ec-3
digital-circuits
sequential-circuit
counters
0
votes
0
answers
6
GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
98
views
gate2016-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
7
GATE ECE 2015 Set 3 | Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
Milicevic3306
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in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
91
views
gate2015-ec-3
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
8
GATE ECE 2015 Set 2 | Question: 16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
162
views
gate2015-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
9
GATE ECE 2015 Set 2 | Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter
Milicevic3306
asked
in
Number Representations
Mar 28, 2018
by
Milicevic3306
15.8k
points
110
views
gate2015-ec-2
digital-circuits
sequential-circuit
counters
0
votes
0
answers
10
GATE ECE 2014 Set 3 | Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch Master-Slave D Flip Flop
Milicevic3306
asked
in
Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
79
views
gate2014-ec-3
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
11
GATE ECE 2014 Set 2 | Question: 41
The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$
Milicevic3306
asked
in
Combinational Circuits
Mar 26, 2018
by
Milicevic3306
15.8k
points
86
views
gate2014-ec-2
digital-circuits
sequential-circuit
flip-flops
0
votes
1
answer
12
GATE ECE 2014 Set 1 | Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
Milicevic3306
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in
Number Representations
Mar 26, 2018
by
Milicevic3306
15.8k
points
265
views
gate2014-ec-1
digital-circuits
sequential-circuit
0
votes
0
answers
13
GATE ECE 2012 | Question: 6
Consider the given circuit. In the circuit, the race around does not occur occurs when $\text{CLK}=0$ occurs when $\text{CLK}=1$ and $A=B=1$ occurs when $\text{CLK}=1$ and $A=B=0$
Milicevic3306
asked
in
Number Representations
Mar 25, 2018
by
Milicevic3306
15.8k
points
101
views
gate2012-ec
digital-circuits
sequential-circuit
flip-flop
0
votes
0
answers
14
GATE ECE 2018 | Question: 46
In the circuit shown below, a positive edge-triggered $D$ Flip-Flop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.
gatecse
asked
in
Number Representations
Feb 19, 2018
by
gatecse
1.5k
points
129
views
gate2018-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
15
GATE ECE 2018 | Question: 19
A traffic signal cycles from $\text{ GREEN to YELLOW, YELLOW to RED and RED to GREEN.}$ In each cycle, $\text{GREEN}$ is turned on for $70$ seconds,$\text{YELLOW}$ is turned on for $5$ seconds and the $\text{RED}$ is turned on $75$ ... $5$ second period. The minimum number of flip-flops required to implement this $\text{FSM}$ is _________.
gatecse
asked
in
Digital Circuits
Feb 19, 2018
by
gatecse
1.5k
points
89
views
gate2018-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
0
votes
0
answers
16
GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
43.6k
points
159
views
gate2017-ec-1
digital-circuits
sequential-circuit
shift-registers
numerical-answers
0
votes
0
answers
17
GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
43.6k
points
205
views
gate2017-ec-1
digital-circuits
sequential-circuit
counters
0
votes
0
answers
18
GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$
admin
asked
in
Number Representations
Nov 17, 2017
by
admin
43.6k
points
111
views
gate2017-ec-1
digital-circuits
sequential-circuit
latch
0
votes
0
answers
19
GATE ECE 2017 Set 1 | Question: 17
Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.
admin
asked
in
Sequential Circuits
Nov 17, 2017
by
admin
43.6k
points
139
views
gate2017-ec-1
digital-circuits
sequential-circuit
latch
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