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Recent questions tagged sequentialcircuit
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GATE EC 2021  Question: 46
The propagation delay of the exclusive$\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flipflops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flipflop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
asked
Feb 20
in
Digital Circuits
by
Arjun
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4.4k
points)

15
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gateec2021
numericalanswers
digitalcircuits
sequentialcircuit
counters
0
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0
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2
GATE ECE 2020  Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setuptime, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
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1.8k
points)

38
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gate2020ec
numericalanswers
digitalcircuits
sequentialcircuit
flipflops
0
votes
0
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3
GATE ECE 2016 Set 3  Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}5\:\text{counter}$ $\text{mod}6\:\text{counter}$ $\text{mod}7\:\text{counter}$ $\text{mod}8\:\text{counter}$
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

30
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gate2016ec3
digitalcircuits
sequentialcircuit
counters
0
votes
0
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4
GATE ECE 2016 Set 2  Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flipflops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

21
views
gate2016ec2
numericalanswers
digitalcircuits
sequentialcircuit
counters
0
votes
0
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5
GATE ECE 2015 Set 3  Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the pushbutton switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

21
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gate2015ec3
digitalcircuits
sequentialcircuit
flipflops
0
votes
0
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6
GATE ECE 2015 Set 2  Question: 16
A mod$n$ counter using a synchronous binary upcounter with synchronous clear input is shown in the figure. The value of $n$ is _______.
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

24
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gate2015ec2
numericalanswers
digitalcircuits
sequentialcircuit
counters
0
votes
0
answers
7
GATE ECE 2015 Set 2  Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod$2$ counter mod$4$ counter mod$5$ counter mod$6$ counter
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

29
views
gate2015ec2
digitalcircuits
sequentialcircuit
counters
0
votes
0
answers
8
GATE ECE 2014 Set 3  Question: 15
The circuit shown in the figure is a Toggle Flip Flop JK Flip Flop SR Latch MasterSlave D Flip Flop
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

21
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gate2014ec3
digitalcircuits
sequentialcircuit
flipflops
0
votes
0
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9
GATE ECE 2014 Set 2  Question: 41
The outputs of the two flipflops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is $01110 \dots$ $01010\dots$ $00110\dots$ $01100\dots$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

37
views
gate2014ec2
digitalcircuits
sequentialcircuit
flipflops
0
votes
1
answer
10
GATE ECE 2014 Set 1  Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

71
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gate2014ec1
digitalcircuits
sequentialcircuit
0
votes
0
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11
GATE ECE 2012  Question: 6
Consider the given circuit. In the circuit, the race around does not occur occurs when $\text{CLK}=0$ occurs when $\text{CLK}=1$ and $A=B=1$ occurs when $\text{CLK}=1$ and $A=B=0$
asked
Mar 25, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

35
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gate2012ec
digitalcircuits
sequentialcircuit
flipflop
0
votes
0
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12
GATE ECE 2018  Question: 46
In the circuit shown below, a positive edgetriggered $D$ FlipFlop is used for sampling input data $D_{in}$ using clock $CK$. The XOR gate output $3.3$ volts for logic HIGH and $0$ volts for logic LOW levels. The data bit and clock periods are ... period is $0.3$, the average value (in volts, accurate to two decimal places) of the voltage at node $X$, is _________.
asked
Feb 19, 2018
in
Digital Circuits
by
gatecse
(
1.5k
points)

59
views
gate2018ec
numericalanswers
digitalcircuits
sequentialcircuit
flipflops
0
votes
0
answers
13
GATE ECE 2018  Question: 19
A traffic signal cycles from $\text{ GREEN to YELLOW, YELLOW to RED and RED to GREEN.}$ In each cycle, $\text{GREEN}$ is turned on for $70$ seconds,$\text{YELLOW}$ is turned on for $5$ seconds and the $\text{RED}$ is turned on $75$ ... $5$ second period. The minimum number of flipflops required to implement this $\text{FSM}$ is _________.
asked
Feb 19, 2018
in
Digital Circuits
by
gatecse
(
1.5k
points)

35
views
gate2018ec
numericalanswers
digitalcircuits
sequentialcircuit
flipflops
0
votes
0
answers
14
GATE ECE 2017 Set 1  Question: 46
A finite state machine (FSM) is implemented using the D flipflop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.8k
points)

111
views
gate2017ec1
digitalcircuits
sequentialcircuit
counters
0
votes
0
answers
15
GATE ECE 2017 Set 1  Question: 44
A $4$bit shift register circuit configured for rightshift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.8k
points)

75
views
gate2017ec1
digitalcircuits
sequentialcircuit
shiftregisters
numericalanswers
0
votes
0
answers
16
GATE ECE 2017 Set 1  Question: 15
In the latch circuit shown, the $NAND$ gates have nonzero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are, $X=’1’$, $Y=’1’$ either $X=’1’$, $Y=’0’$ or $X=’0’$, $Y=’1’$ either $X=’1’$, $Y=’1’$ or $X=’0’$, $Y=’0’$ $X=’0’$, $Y=’0’$
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.8k
points)

55
views
gate2017ec1
digitalcircuits
sequentialcircuit
latch
0
votes
0
answers
17
GATE ECE 2017 Set 1  Question: 17
Consider the DLatch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a onefifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.8k
points)

53
views
gate2017ec1
digitalcircuits
sequentialcircuit
latch
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