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GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and ...
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May 24, 2018
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