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GATE ECE 2007 | Question-44

The following binary values were applied to the $\mathrm{X}$ and $\mathrm{Y}$ inputs of the NAND latch shown in the figure in the sequence indicated below:
\[ \mathrm{X}=0, \mathrm{Y}=1 ; \quad \mathrm{X}=0, \mathrm{Y}=0 ; \quad \mathrm{X}=1, \mathrm{Y}=1 \text {.} \]

The corresponding stable $\mathrm{P}, \mathrm{Q}$ outputs will be

  1. $\mathrm{P}=1, \mathrm{Q}=0 ; \qquad \mathrm{P}=1, \mathrm{Q}=0 ; \qquad \qquad \qquad \qquad \mathrm{P}=1, \mathrm{Q}=0$ or $\mathrm{P}=0, \mathrm{Q}=1$
  2. $\mathrm{P}=1, \mathrm{Q}=0 ; \qquad \mathrm{P}=0, \mathrm{Q}=1$ or $\mathrm{P}=0, \mathrm{Q}=1; \; \quad \mathrm{P}=0, \mathrm{Q}=1$
  3. $\mathrm{P}=1, \mathrm{Q}=0 ; \qquad \mathrm{P}=1, \mathrm{Q}=1 ; \qquad \qquad \qquad \qquad\mathrm{P}=1, \mathrm{Q}=0$ or $\mathrm{P}=0, \mathrm{Q}=1$
  4. $\mathrm{P}=1, \mathrm{Q}=0 ; \qquad \mathrm{P}=1, \mathrm{Q}=1 ; \qquad \qquad \qquad \qquad  \mathrm{P}=1, \mathrm{Q}=1$
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