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GATE ECE 2004 | Question-17

Figure given below shows the internal schematic of a $\text{TTL AND-OR}$ -Invert $\text{(AOI)}$ gate. For the inputs shown in the given figure, the output $\text{Y}$ is
 

  1. $0$
  2. $1$
  3. $\mathrm{AB}$
  4. $\overline{\mathrm{AB}}$
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