A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip flops having a propagation delay of $10 \mathrm{~ns}$ each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then
- $\mathrm{R}=10 \mathrm{~ns}, \mathrm{~S}=40 \mathrm{~ns}$
- $\mathrm{R}=40 \mathrm{~ns}, \mathrm{~S}=10 \mathrm{~ns}$
- $\mathrm{R}=10 \mathrm{~ns}, \mathrm{~S}=30 \mathrm{~ns}$
- $\mathrm{R}=30 \mathrm{~ns}, \mathrm{~S}=10 \mathrm{~ns}$