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For the circuit shown in the figure, P and Q are the inputs and Y is the output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The logic implemented by the circuit is

  1. XNOR             
  2. XOR
  3. NOR
  4. OR

 

 

 

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