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Recent questions tagged logic-gates

3 3 votes
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GATE ECE 2026 | Question: 10
In the circuit shown in the Figure, $A$ and $B$ are logic inputs and $Y$ is the logic output.Which of the following logic operations is realized by the circuit?NORORXORAN...
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GATE ECE 2026 | Question: 38
A Boolean function, $f(x, y, z)$ with $x$ as MSB and $z$ as LSB is realized by $4: 1$ multiplexer (MUX) with select lines, $\mathrm{S}_{1}$ and $\mathrm{S}_{0}\left(\math...
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GATE ECE 1997 | Question 2.7
In standard $\text{TTL}$, the 'totem pole' stage refers tothe multi-emitter input stagethe phase splitterthe output bufferopen collector output stage
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GATE ECE 1997 | Question 2.9
The output of the logic gate in the figure is$0$$1$$\text{A}$$\mathrm{F}$
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GATE ECE 1997 | Question 4.7
For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is$\overline{\mathrm{ABCDE}}$$(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\...
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GATE ECE 2000 | Question 1.19
For the logic circuit shown in the figure is the required input condition $(A, B, C)$ to make the output $(X)=1$ is$1,0,1$$0,0,1$$1,1,1$$0,1,1$
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GATE ECE 2000 | Question 15
The operating conditions $(O N=1, O F F=0)$ of three pumps $(x, y, z)$ are to be monitored. $x=1$ implies that pump $X$ is on. It is required that the indicator $\text{(L...
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GATE ECE 1999 | Question 1.10
The logical expresion $y=\mathrm{A}+\overline{\mathrm{A}} \mathrm{B} $ is equivalent to$y=\mathrm{AB}$$y=\overline{\mathrm{A}} \mathrm{B}$$y=\bar{A}+\mathrm{B}$$y=\mathr...
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GATE ECE 1999 | Question 2.11
For a binary half-subtractor having two inputs $\text{A}$ and $\text{B}$, the correct set of logical expressions for the outputs $\text{D}$ ( = $\text{A}$ minus $\text{B}...
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GATE ECE 1999 | Question 12
In a certain application, four inputs $A, B, C, D$ (both true and complement forms available) are fed to logic circuit, producing an output $F$ which operates a relay. Th...
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GATE ECE 2001 | Question: 2.11
In the TTL circuit in the figure, $\mathrm{S}_{2}$ to $\mathrm{S}_{0}$ are select lines and $\text{X}_{7}$ to $\text{X}_{0}$ are input lines. $\text{S}_{0}$ and $\text{X}...
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GATE ECE 2001 | Question: 11
For the digital block shown in the figure the output $\mathrm{Y}=f\left(\mathrm{~S}_{3}, \mathrm{~S}_{2}, \mathrm{~S}_{1}, \mathrm{~S}_{0}\right)$ where $\mathrm{S}_{3}$ ...
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GATE ECE 2002 | Question: 2.10
The circuit in the figure is has two $\text{CMOS NOR}$-gates. This circuit functions as aflip-flopschmitt triggernonostable multivibratorastable multivibrator
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GATE ECE 2002 | Question: 9
The inputs to a digital circuit shown in the figure is are the external signals $A, B$ and $C$.$(\overline{\mathrm{A}}, \overline{\mathrm{B}}$ and $\overline{\mathrm{C}}$...
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GATE ECE 1998 | Question 2.1
The minimum number of $2$-input $\text{NAND}$ gates required to implement the Boolean function $Z=A \bar{B} C$, assiming that $A, B$ and $C$ are available, istwothreefive...
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GATE ECE 2003 | Question: 18
The output of the $74$ series of $\text{TTL}$ gates is taken from a $\text{BJT}$ intotem pole and common collector configurationeither totem pole or open collector config...
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GATE ECE 2004 | Question: 17
Figure given below shows the internal schematic of a $\text{TTL AND-OR}$ -Invert $\text{(AOI)}$ gate. For the inputs shown in the given figure, the output $\text{Y}$ is $...
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GATE ECE 1995 | Question 1.28
The output of the circuit in the figure is equal to$0$$1$$\overline{\mathrm{A}} \mathrm{B}+\mathrm{A} \overline{\mathrm{B}}$$\overline{(\mathrm{A} * \mathrm{~B})} * \over...
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GATE ECE 1995 | Question 3.5
For a $\text{TTL}$ gate, match the following(A) $\mathrm{V}_{\mathrm{OH}}$ $\text{(min)}$(B) $\mathrm{V}_{\mathrm{IH}}$ $\text{(min)}$(C) $\mathrm{V}_{\mathrm{OL}}$ $\tex...
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GATE ECE 1996 | Question 1.10
Schottky clamping is resorted in $\text{TTL}$ gatesto reduce propagation delayto increase noise marginsto increase packing densityto increase fan-out
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GATE ECE 2006 | Question: 49
The point $\text{P}$ in the following figure is stuck-at-$1$. The output $f$ will be$\overline{\mathrm{AB} \overline{\mathrm{C}}}$$\overline{\mathrm{A}}$$\mathrm{AB} \ove...
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GATE ECE 1994 | Question 1.11
The output of a logic gate is ‘$1$’ when all its inputs are at logic ‘$0$’. Then gate is eithera $\text{NAND}$ or an $\text{EX-OR}$ gatea $\text{NOR}$ or an $\text{EX-NOR...
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GATE ECE 2007 | Question: 42
The circuit diagram of a standard $\text{TTL NOT}$ gate is shown in the figure. When $V_{i}=2.5 \mathrm{~V},$ the modes of operation of the transistors will be$\mathrm{Q}...
1 1 vote
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GATE ECE 2007 | Question: 43
In the following circuit, $X$ is given by$X=A \overline{B}\; \overline{C}+\overline{A} B \overline{C}+\overline{A}\; \overline{B} C+A B C$$X=\overline{A} B C+A \overline{...
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GATE ECE 2007 | Question: 44
The following binary values were applied to the $\mathrm{X}$ and $\mathrm{Y}$ inputs of the NAND latch shown in the figure in the sequence indicated below:\[ \mathrm{X}=0...
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GATE ECE 2008 | Question: 54
The logic function implemented by the following circuit at the terminal $\text{OUT}$ is$\text{P NOR Q}$$\text{P NAND Q}$$\text{P OR Q}$$\text{P AND Q}$
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GATE ECE 1993 | Question 4.8
For the logic circuit shown in the figure is the output $Y$ is equal to$\overline{\mathrm{ABC}}$$\overline{\mathrm{A}}+\overline{\mathrm{B}}+\overline{\mathrm{C}}$$\overl...
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GATE ECE 1993 | Question 6.13
Boolean expression for the output of $\text{XNOR}$ (Equivalent) logic gate with inputs $A$ and $B$ is$\mathrm{A} \overline{\mathrm{B}}+\overline{\mathrm{A}} \mathrm{B}$$\...
1 1 vote
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GATE ECE 2009 | Question: 6
The full forms of the abbreviations $\text{TTL}$ and $\text{CMOS}$ in reference to logic families areTriple Transistor Logic and Chip Metal Oxide SemiconductorTristate Tr...
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1 answers 1 answer
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GATE ECE 2009 | Question: 38
Refer to the NAND and NOR latches shown in the figure. The inputs $\left(P_{1}, P_{2}\right)$ for both the latches are first made $(0,1)$ and then, after a few seconds, m...
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