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Recent questions tagged logicgates
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1
GATE2019 EC: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR
asked
Feb 12, 2019
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Arjun
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1.4k
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gate2019ec
digitalcircuits
logicgates
0
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2
GATE2016317
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
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Mar 28, 2018
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Milicevic3306
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15.7k
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gate2016ec3
digitalcircuits
logicgates
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3
GATE2016318
The minimum number of $2$input $NAND$ gates required to implement a $2$input $XOR$ gate is $4$ $5$ $6$ $7$
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Mar 28, 2018
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Milicevic3306
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gate2016ec3
digitalcircuits
logicgates
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4
GATE2016344
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
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Mar 28, 2018
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Milicevic3306
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gate2016ec3
numericalanswers
norgates
digitalcircuits
logicgates
0
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0
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5
GATE2016345
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}5\:\text{counter}$ $\text{mod}6\:\text{counter}$ $\text{mod}7\:\text{counter}$ $\text{mod}8\:\text{counter}$
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Mar 28, 2018
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by
Milicevic3306
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15.7k
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gate2016ec3
digitalcircuits
logicgates
nandgate
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0
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6
GATE2015315
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$input OR gate $3$input NOR gate $3$input AND gate $3$input XOR gate
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Mar 28, 2018
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by
Milicevic3306
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gate2015ec3
digitalcircuits
logicgates
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0
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7
GATE2015337
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate
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Mar 28, 2018
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Milicevic3306
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gate2015ec3
digitalcircuits
logicgates
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8
GATE2015338
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the pushbutton switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
asked
Mar 28, 2018
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Milicevic3306
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15.7k
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gate2015ec3
digitalcircuits
logicgates
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9
GATE2015214
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
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Mar 28, 2018
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gate2015ec2
digitalcircuits
logicgates
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10
GATE2015138
A $3$input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(a,b,\overline{c}),c)$? $3$input NAND gate $3$input XOR gate $3$input NOR gate $3$input XNOR gate
asked
Mar 28, 2018
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by
Milicevic3306
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15.7k
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gate2015ec1
digitalcircuits
logicgates
0
votes
1
answer
11
GATE2014142
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ ... $Q2$ Input $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
asked
Mar 26, 2018
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Milicevic3306
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gate2014ec1
logicgates
digitalcircuits
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12
GATE201847
The logic gates shown in the digital circuit below use strong pulldown $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pulldowns are off, highvalue resistors set the output logic levels to HIGH (i.e. the pullups are weak). Note that some nodes are ... distinct values of $X_{3}X_{2}X_{1}X_{0}$ (out of the $16$ possible values) that give $Y=1$ is ________.
asked
Feb 19, 2018
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gatecse
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1.4k
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gate2018ec
numericalanswers
digitalcircuits
logicgates
0
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13
GATE20188
The logic function $f(X, Y)$ realized by the given circuit is NOR AND NAND XOR
asked
Feb 19, 2018
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gatecse
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1.4k
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gate2018ec
logicgates
digitalcircuits
+1
vote
2
answers
14
GATE2017 EC2: 44
Figure Ⅰ shows a $4$bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a fulladder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume all ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
asked
Nov 25, 2017
in
Digital Circuits
by
admin
(
2.8k
points)
gate2017ec2
numericalanswers
logicgates
digitalcircuits
0
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0
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15
GATE2017 EC2: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR
asked
Nov 23, 2017
in
Digital Circuits
by
admin
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2.8k
points)
gate2017ec2
logicgates
digitalcircuits
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