Recent questions tagged digital-circuits - GO Electronics

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GATE2020-EC: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from mid-bandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$

asked Feb 13 in Others by jothee (1.4k points)

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GATE2020-EC: 10
The figure below shows a multiplexer where $S_{1}$ and $S{2}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$

asked Feb 13 in Others by jothee (1.4k points)

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3

GATE2020-EC: 19
In an $8085$ microprocessor, the number of address lines required to access a $\text{16 K byte}$ memory bank is ____________ .

asked Feb 13 in Others by jothee (1.4k points)

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4

GATE2020-EC: 20
A $\text{10-bit D/A}$ converter is calibrated over the full range from $\text{0 to 10 V}$. If the input to the $\text{D/A}$ converter is $\text{13A}$ (in hex), the output ( rounded off to three decimal places) is __________ $\text{V}$.

asked Feb 13 in Others by jothee (1.4k points)

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5

GATE2020-EC: 32
The band diagram of a $\text{p-type}$ semiconductor with a band-gap of $\text{1 eV}$ is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $\text{-0.16 V}$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87\:eV$ is fabricated. There is ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$

asked Feb 13 in Others by jothee (1.4k points)

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6

GATE2019 EC: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR

asked Feb 12, 2019 in Others by Arjun (1.4k points)

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7

GATE2016-3-10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ and $E_{gZ}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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8

GATE2016-3-16
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be $4E$ and $0$ $4E$ and $1$ $4F$ and $0$ $4F$ and $1$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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9

GATE2016-3-17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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10

GATE2016-3-18
The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is $4$ $5$ $6$ $7$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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11

GATE2016-3-43
Following is the K-map of a Boolean function of five variables $P,Q,R,S$ and $X$ ... $\overline{Q}\:S\:X+\;Q\:\overline{S}\:\overline{X}$ $\overline{Q}\:S+\;Q\overline{S}$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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12

GATE2016-3-44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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13

GATE2016-3-45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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14

GATE2016-2-17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with logic values $0,1,0,1$ and $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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15

GATE2016-2-18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select bit. Which one ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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16

GATE2016-2-19
The response of the system $G(s)=\frac{s-2}{(s+1)(s+3)}$ to the unit step input $u(t)$ is $y(t)$. The value of $\frac{dy}{dt}$ at $t=0^{+}$ is _________

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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17

GATE2016-2-42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, where $A_{15}$ ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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18

GATE2016-2-43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ (whose output is ... the maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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19

GATE2016-2-44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State $A$ are ... from State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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20

GATE2016-1-11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent atoms to ... pentavalent atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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21

GATE2016-1-12
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): As channel length reduces,OFF-state current increases. As channel length reduces,output resistance increases. As channel length reduces,threshold voltage remains constant. As channel length ... increases. Which of the above statements are INCORRECT? P and Q P and S Q and R R and S

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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22

GATE2016-1-43
The functionality implemented by the circuit below is $2$-to-$1$ multiplexer $4$-to-$1$ multiplexer $7$-to-$1$ multiplexer $6$-to-$1$ multiplexer

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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23

GATE2016-1-44
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this? For POP, the data transceivers remain in the same direction as for instruction fetch (memory to ... already in the stack pointer. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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24

GATE2015-3-15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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25

GATE2015-3-16
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$ ...

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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26

GATE2015-3-37
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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27

GATE2015-3-38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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28

GATE2015-2-14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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29

GATE2015-2-15
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator? MOV B, M PCHL RNZ SBI BEH

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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30

GATE2015-2-16
A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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31

GATE2015-2-37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-$6$ counter

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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32

GATE2015-2-38
A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$-to-$4$ decoders (with enable input $\overline{E}$ and address ... $D_{in}, S_{0}, S_{1}, S_{2} $ $D_{in}, S_{2}, S_{0}, S_{1}$

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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33

GATE2015-2-39
The diode in the circuit given below has $V_{ON} = 0.7\:V$ but is ideal otherwise. The current $(\text{in}\: mA)$ in the $4\: k\Omega$ resistor is _______.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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34

GATE2015-1-14
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively B and F A and F H and F A and C

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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35

GATE2015-1-15
A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ___________

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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36

GATE2015-1-16
Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog value (in Volts) corresponding to the digital signal $1111$ is _________

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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37

GATE2015-1-24
Consider a straight, infinitely long, current carrying conductor lying on the z-axis. Which one of the following plots (in linear scale) qualitatively represents the dependence of $H_{\phi}$ on $r$, where $H_{\phi}$ is the magnitude of the azimuthal component of magnetic field outside the conductor and $r$ is the radial distance from the conductor?

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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38

GATE2015-1-38
A $3$-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(a,b,\overline{c}),c)$? $3$-input NAND gate $3$-input XOR gate $3$-input NOR gate $3$-input XNOR gate

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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39

GATE2015-1-42
In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\circ}C$, the value of the voltage $V_{12}=V_1 - V_2$ (in mV) is _______.

asked Mar 28, 2018 in Others by Milicevic3306 (15.7k points)

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40

GATE2014-4-14
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then droop rate decreases and acquisition time decreases droop rate decreases and acquisition time increases droop rate increases and acquisition time decreases droop rate increases and acquisition time increases

asked Mar 26, 2018 in Others by Milicevic3306 (15.7k points)

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