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Answers by Vidhya16
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GATE ECE 2009 | Question: 58
Consider the CMOS circuit shown, where the gate voltage $V_{G}$ of the $\text{n-MOSFET}$ is increased from zero, while the gate voltage of the $\text{p-MOSFET}$ is kept constant at $3 \mathrm{~V}$ ... $4-\frac{\sqrt{3}}{2} \mathrm{~V}$ $4+\frac{\sqrt{3}}{2} \mathrm{~V}$
Consider the CMOS circuit shown, where the gate voltage $V_{G}$ of the $\text{n-MOSFET}$ is increased from zero, while the gate voltage of the $\text{p-MOSFET}$ is kept c...
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