Electronis Discussion
0 votes

Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.

 

in Digital Circuits by (2.8k points)
retagged by

Please log in or register to answer this question.

Answer:
Welcome to GO Electronics, where you can ask questions and receive answers from other members of the community.
1,109 questions
52 answers
8 comments
43,015 users