Register

GATE ECE 2017 Set 1 | Question: 17

• recategorized by
1,047 views
1 1 vote

Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.

1 Answer

Answer:
← Previous · GATE ECE 2017 Set 1 ...Next → · GATE ECE 2017 Set 1 ...
Next in category → · GATE ECE 2012 | Ques...
Position:
Show:
Voting & Accepting an answer helps improve the community

Related questions

1 1 vote
1 answers 1 answer
1.5k
1.5k views
admin asked Nov 17, 2017
1,538 views
GATE ECE 2017 Set 1 | Question: 15
In the latch circuit shown, the $NAND$ gates have non-zero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed si...
0 0 votes
0 0 answers
1.1k
1.1k views
admin asked Nov 17, 2017
1,103 views
GATE ECE 2017 Set 1 | Question: 46
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_...
0 0 votes
0 0 answers
843
843 views
admin asked Nov 17, 2017
843 views
GATE ECE 2017 Set 1 | Question: 44
A $4$-bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present s...
0 0 votes
0 0 answers
1.2k
1.2k views
Milicevic3306 asked Mar 27, 2018
1,190 views
GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, ...

Add Synced Question

×