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An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by

  1. $Y = A \: \overline{B} \:C+A \: \overline{C}  \:D$
  2. $Y  = \overline{A} \: B \:C +A \: \overline{B} \: D$
  3. $Y = A \: B \: \overline{C} + \overline{A}  \: C \:D$
  4. $Y= \overline{A} \: \overline{B} \: D + A  \: \overline{B}  \: C$
in Digital Circuits by (15.8k points)
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