Electronis Discussion

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An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by

- $Y = A \: \overline{B} \:C+A \: \overline{C} \:D$
- $Y = \overline{A} \: B \:C +A \: \overline{B} \: D$
- $Y = A \: B \: \overline{C} + \overline{A} \: C \:D$
- $Y= \overline{A} \: \overline{B} \: D + A \: \overline{B} \: C$

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