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GATE ECE 2014 Set 4 | Question: 41

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A $16$ – bit ripple carry adder is realized using $16$ identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is $12$ ns and the sum-propagation delay of each FA is $15$ ns. The worst case delay (in ns) of this $16$-bit adder will be _______

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