Recent questions tagged multiplexers

​​​​​The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$.If $\text...

In the circuit shown below, $\mathrm{P}$ and $\mathrm{Q}$ are the inputs. The logical function realized by the circuit shown below is$\mathrm{Y}=\mathrm{PQ}$$\mathrm{Y}=\...

The Boolean function realized by the logic circuit shown is$\text{F} = \sum_{\text{m}} (0, 1, 3, 5, 9, 10, 14)$$\text{F}=\sum_{\text{m}}(2,3,5,7,8,12,13)$$\text{F}=\sum_{...

The logic function implemented by the circuit below is (ground implies a logic $\text{“0”})$$\text{F=AND(P,Q})$$\text{F=OR(P,Q})$$\text{F=XNOR(P,Q})$$\text{F=XOR(P,Q})$

Consider the $ \text{2–bit}$ multiplexer $\text{(MUX)}$ shown in the figure. For $\text{OUTPUT}$ to be the $\text{XOR}$ of $\text{C}$ and $\text{D},$ the values for $A_{0...

The figure below shows a multiplexer where $S_{1}$ and $S_{0}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\te...

An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by$Y = A \: \overline{B} \:C+A \: \overline{C} \:D...

Consider the multiplexer based logic circuit shown in the figure.Which one of the following Boolean functions is realized by the circuit?$F= W \overline{S_1} \: \overline...

In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by$F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$$F= W\overline{X}+\ov...

A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure.The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overli...

Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is$\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $$\overlin...