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Recent questions tagged combinationalcircuits
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GATE ECE 2021  Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$
asked
Feb 20
in
Digital Circuits
by
Arjun
(
4.5k
points)

50
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gateec2021
digitalcircuits
combinationalcircuits
decoders
0
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0
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2
GATE ECE 2021  Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$
asked
Feb 20
in
Digital Circuits
by
Arjun
(
4.5k
points)

67
views
gateec2021
digitalcircuits
combinationalcircuits
multiplexers
0
votes
1
answer
3
GATE ECE 2020  Question: 10
The figure below shows a multiplexer where $S_{1}$ and $S{2}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
(
1.9k
points)

99
views
gate2020ec
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
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4
GATE ECE 2016 Set 3  Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

44
views
gate2016ec3
digitalcircuits
combinationalcircuits
logicgates
0
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0
answers
5
GATE ECE 2016 Set 3  Question: 18
The minimum number of $2$input $NAND$ gates required to implement a $2$input $XOR$ gate is $4$ $5$ $6$ $7$
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

35
views
gate2016ec3
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
6
GATE ECE 2016 Set 3  Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

39
views
gate2016ec3
numericalanswers
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
7
GATE ECE 2016 Set 2  Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

44
views
gate2016ec2
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
answers
8
GATE ECE 2016 Set 1  Question: 43
The functionality implemented by the circuit below is $2$to$1$ multiplexer $4$to$1$ multiplexer $7$to$1$ multiplexer $6$to$1$ multiplexer
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

47
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gate2016ec1
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
answers
9
GATE ECE 2015 Set 3  Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$input OR gate $3$input NOR gate $3$input AND gate $3$input XOR gate
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

33
views
gate2015ec3
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
10
GATE ECE 2015 Set 3  Question: 37
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

38
views
gate2015ec3
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
11
GATE ECE 2015 Set 2  Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

41
views
gate2015ec2
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
12
GATE ECE 2015 Set 2  Question: 38
A $1$to$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$to$4$ ... $D_{in}, S_{0}, S_{1}, S_{2} $ $D_{in}, S_{2}, S_{0}, S_{1}$
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

38
views
gate2015ec2
digitalcircuits
combinationalcircuits
decoders
0
votes
0
answers
13
GATE ECE 2014 Set 4  Question: 15
In the circuit shown in the figure, if $C=0$, the expression for $Y$ is $Y=A \overline{B} + \overline{A}B$ $Y=A+B$ $Y=\overline{A} + \overline{B}$ $Y=A \: B$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

34
views
gate2014ec4
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
14
GATE ECE 2014 Set 4  Question: 40
An $8$ to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by $Y = A \: \overline{B} \:C+A \: \overline{C} \:D$ $Y = \overline{A} \: B \:C +A \: \overline{B} \: D$ $Y = A \: B \: \overline{C} + \overline{A} \: C \:D$ $Y= \overline{A} \: \overline{B} \: D + A \: \overline{B} \: C$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

42
views
gate2014ec4
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
answers
15
GATE ECE 2014 Set 3  Question: 16
Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit? $F= W \overline{S_1} \: \overline{S_2}$ $F= WS_1+WS_2 + S_{1}S_{2}$ $F= \overline{W}+S_{1}+S_{2}$ $F= W\oplus S_{1}\oplus S_{2}$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

32
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gate2014ec3
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
answers
16
GATE ECE 2014 Set 3  Question: 41
In the circuit shown, $W$ and $Y$ are MSBs of the control inputs. The output $F$ is given by $F= W\overline{X}+\overline{W}X+\overline{Y}\overline{Z}$ $F= W\overline{X}+\overline{W}X+\overline{Y}Z$ $F= W\overline{X}\overline{Y}+\overline{W}X\overline{Y}$ $F= ( \overline{W}+\overline{X} )\overline{Y}\overline{Z}$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

41
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gate2014ec3
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
answers
17
GATE ECE 2014 Set 3  Question: 42
If $X$ and $Y$ are inputs and the Difference $(D=XY)$ and the Borrow $(B)$ are the outputs, which one of the following diagrams implements a halfsubtractor?
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

46
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gate2014ec3
digitalcircuits
combinationalcircuits
halfsubtractorcircuit
multiplexers
0
votes
0
answers
18
GATE ECE 2014 Set 2  Question: 16
In a halfsubtractor circuit with $X$ and $Y$ as inputs, the Borrow $(M)$ and Difference $(N = X – Y)$ are given by $M = X \oplus Y, \: \: \: N = XY$ $M = XY, \: \: \:N = X \oplus Y$ $M = \overline{ X}Y, \: \: \: N =X \oplus Y$ $M = X \overline{ Y}, \: \: \: N = \overline{X \oplus Y}$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

25
views
gate2014ec2
digitalcircuits
combinationalcircuits
halfsubtractorcircuit
0
votes
0
answers
19
GATE ECE 2014 Set 2  Question: 42
For the $8085$ microprocessor, the interfacing circuit to input $8$bit digital data $( DI_{0}DI_{7})$ from an external device is shown in the figure. The instruction for correct data transfer is $\text{MVI A, F8H}$ $\text{IN F8H}$ $\text{OUT F8H}$ $\text{LDA F8F8H}$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

55
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gate2014ec2
digitalcircuits
combinationalcircuits
microprocessor8085
0
votes
0
answers
20
GATE ECE 2014 Set 1  Question: 40
The output $F$ in the digital logic circuit shown in the figure is $F = \overline{X}\:Y\:Z + X\:\overline{Y}\:Z$ $F = \overline{X}\:Y\:\overline{Z} + X\:\overline{Y}\:\overline{Z}$ $F = \overline{X}\:\overline{Y}\:Z + X\:Y\:Z$ $F = \overline{X}\:\overline{Y}\:\overline{Z} + X\:Y\:Z$
asked
Mar 26, 2018
in
Digital Circuits
by
Milicevic3306
(
15.8k
points)

39
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gate2014ec1
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
21
GATE ECE 2018  Question: 47
The logic gates shown in the digital circuit below use strong pulldown $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pulldowns are off, highvalue resistors set the output logic levels to HIGH (i.e. the pullups are weak). Note that some nodes ... values of $X_{3}X_{2}X_{1}X_{0}$ (out of the $16$ possible values) that give $Y=1$ is ________.
asked
Feb 19, 2018
in
Digital Circuits
by
gatecse
(
1.5k
points)

84
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gate2018ec
numericalanswers
digitalcircuits
combinationalcircuits
logicgates
+1
vote
1
answer
22
GATE ECE 2018  Question: 31
A fourvariable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$
asked
Feb 19, 2018
in
Digital Circuits
by
gatecse
(
1.5k
points)

104
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gate2018ec
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
answers
23
GATE ECE 2018  Question: 8
The logic function $f(X, Y)$ realized by the given circuit is NOR AND NAND XOR
asked
Feb 19, 2018
in
Digital Circuits
by
gatecse
(
1.5k
points)

46
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gate2018ec
digitalcircuits
combinationalcircuits
logicgates
+1
vote
0
answers
24
GATE ECE 2017 Set 2  Question: 45
A programmable logic array (PLA) is shown in the figure. The Boolean function $F$ implemented is $\overline{P} \: \overline{Q}R+ \overline{P}QR+P \overline{Q} \: \overline{R}$ $(\overline{P}+\overline{Q}+R)(\overline{P}+Q+R)(P+\overline{Q}+\overline{R})$ ... $(\overline{P}+\overline{Q}+R)(\overline{P}+Q+R)(P+\overline{Q}+R)$
asked
Nov 25, 2017
in
Digital Circuits
by
admin
(
2.8k
points)

112
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gate2017ec2
digitalcircuits
combinationalcircuits
logicgates
+1
vote
2
answers
25
GATE ECE 2017 Set 2  Question: 44
Figure Ⅰ shows a $4$bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a fulladder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
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Nov 25, 2017
in
Digital Circuits
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admin
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1.5k
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gate2017ec2
numericalanswers
digitalcircuits
combinationalcircuits
adder
0
votes
0
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26
GATE ECE 2017 Set 2  Question: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $\overline{X} \overline{Y} \overline{Z} + X Y +\overline{Y} Z $ $\overline{X} Y \overline{Z} + X Z + \overline{Y} Z $ $\overline{X} Y \overline{Z} +XY + \overline{Y} Z $ $\overline{X} \overline{Y} \overline{Z} + XZ+ \overline{Y}Z $
asked
Nov 23, 2017
in
Digital Circuits
by
admin
(
2.8k
points)

69
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gate2017ec2
digitalcircuits
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