in Digital Circuits retagged by
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In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively,

  1. NOR, OR
  2. OR, NAND
  3. NAND, OR
  4. AND,NAND
in Digital Circuits retagged by
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