• recategorized by
814 views
0 0 votes

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

  1. NOR gates to NAND gates
  2. inverters to buffers
  3. NOR gates to NAND gates and inverters to buffers
  4. $5\: V$ to ground

Please log in or register to answer this question.

Answer:
Position:
Show:

Related questions

0 0 votes
0 0 answers
692
692 views
Milicevic3306 asked Mar 26, 2018
692 views
The circuit shown in the figure is a Toggle Flip FlopJK Flip FlopSR LatchMaster-Slave D Flip Flop
0 0 votes
0 0 answers
699
699 views
Milicevic3306 asked Mar 27, 2018
699 views
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$...
2 2 votes
1 answers 1 answer
2.1k
2.1k views
Milicevic3306 asked Mar 27, 2018
2,060 views
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown.Which one of the following statemen...
2 2 votes
1 1 answer
3.1k
3.1k views
go_editor asked Feb 13, 2020
3,117 views
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time....

Add Synced Question

×