GATE ECE 2015 Set 1 | Question: 37

Question

All the logic gates shown in the figure have a propagation delay of $20$ ns. Let $A=C=0$ and $B=1$ until time $t=0$. At $t=0$, all the inputs flip (i.e., $A=C=1$ and $B=0$) and remain in that state. For $t>0$, output $Z=1$ for a duration (in ns) of ________.