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Recent questions and answers in Digital Circuits
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GATE ECE 2021  Question: 11
If $(1235)_{x}\:=\:(3033)_{y}$, where $x$ and $y$ indicate the bases of the corresponding numbers, then $x\:=\:7$ and $y\:=\:5$ $x\:=\:8$ and $y\:=\:6$ $x\:=\:6$ and $y\:=\:4$ $x\:=\:9$ and $y\:=\:7$
asked
Feb 20
in
Digital Circuits
by
Arjun
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4.5k
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87
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gateec2021
digitalcircuits
numbersystem
numberrepresentation
0
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0
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2
GATE ECE 2021  Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$
asked
Feb 20
in
Digital Circuits
by
Arjun
(
4.5k
points)

50
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gateec2021
digitalcircuits
combinationalcircuits
decoders
0
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0
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3
GATE ECE 2021  Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$
asked
Feb 20
in
Digital Circuits
by
Arjun
(
4.5k
points)

67
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gateec2021
digitalcircuits
combinationalcircuits
multiplexers
0
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0
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4
GATE ECE 2021  Question: 46
The propagation delay of the exclusive$\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flipflops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flipflop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
asked
Feb 20
in
Digital Circuits
by
Arjun
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4.5k
points)

36
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gateec2021
numericalanswers
digitalcircuits
sequentialcircuit
counters
0
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2
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5
GATE ECE 2014 Set 1  Question: 15
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to $X$ $Y$ $XY$ $X+Y$
answered
Jan 5
in
Digital Circuits
by
Hira Thakur
(
240
points)

82
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gate2014ec1
digitalcircuits
booleanalgebra
+1
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1
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6
GATE ECE 2018  Question: 31
A fourvariable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$
answered
Jan 5
in
Digital Circuits
by
Hira Thakur
(
240
points)

104
views
gate2018ec
digitalcircuits
combinationalcircuits
multiplexers
0
votes
1
answer
7
GATE ECE 2020  Question: 10
The figure below shows a multiplexer where $S_{1}$ and $S{2}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$
answered
Jan 5
in
Digital Circuits
by
Hira Thakur
(
240
points)

99
views
gate2020ec
digitalcircuits
combinationalcircuits
multiplexers
0
votes
1
answer
8
GATE ECE 2014 Set 1  Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
answered
May 19, 2020
in
Digital Circuits
by
srestha
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460
points)

95
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gate2014ec1
digitalcircuits
sequentialcircuit
0
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0
answers
9
GATE ECE 2020  Question: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from midbandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
(
1.9k
points)

73
views
gate2020ec
digitalcircuits
semiconductor
0
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0
answers
10
GATE ECE 2020  Question: 19
In an $8085$ microprocessor, the number of address lines required to access a $16$ K byte memory bank is ____________ .
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
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1.9k
points)

46
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gate2020ec
numericalanswers
digitalcircuits
microprocessor8085
0
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0
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11
GATE ECE 2020  Question: 20
A $10$bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
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1.9k
points)

69
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gate2020ec
numericalanswers
digitalcircuits
dataconverters
0
votes
0
answers
12
GATE ECE 2020  Question: 32
The band diagram of a $p$type semiconductor with a bandgap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{8}$ $0.52\times 10^{8}$ $1.41\times 10^{8}$ $0.93\times 10^{8}$
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
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1.9k
points)

73
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gate2020ec
digitalcircuits
semiconductor
0
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0
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13
GATE ECE 2020  Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setuptime, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
asked
Feb 13, 2020
in
Digital Circuits
by
jothee
(
1.9k
points)

85
views
gate2020ec
numericalanswers
digitalcircuits
sequentialcircuit
flipflops
0
votes
0
answers
14
GATE ECE 2019  Question: 14
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively? $\text{0 and D}$ $\text{HiZ and D}$ $\text{0 and 1}$ $\text{HiZ and}$ $ \overline{D}$
asked
Feb 12, 2019
in
Digital Circuits
by
Arjun
(
4.5k
points)

73
views
gate2019ec
digitalcircuits
logicgates
0
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0
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15
GATE ECE 2019  Question: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR
asked
Feb 12, 2019
in
Digital Circuits
by
Arjun
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4.5k
points)

78
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gate2019ec
digitalcircuits
logicgates
+1
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2
answers
16
GATE ECE 2017 Set 2  Question: 44
Figure Ⅰ shows a $4$bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a fulladder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
answered
Aug 29, 2018
in
Digital Circuits
by
Amit puri
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140
points)

1.5k
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gate2017ec2
numericalanswers
digitalcircuits
combinationalcircuits
adder
0
votes
0
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17
GATE ECE 2016 Set 3  Question: 10
The $IV$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

50
views
gate2016ec3
digitalcircuits
semiconductor
0
votes
0
answers
18
GATE ECE 2016 Set 3  Question: 16
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be $4E$ and $0$ $4E$ and $1$ $4F$ and $0$ $4F$ and $1$
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Mar 28, 2018
in
Digital Circuits
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Milicevic3306
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15.8k
points)

29
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gate2016ec3
digitalcircuits
microprocessor8085
0
votes
0
answers
19
GATE ECE 2016 Set 3  Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
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Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

44
views
gate2016ec3
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
20
GATE ECE 2016 Set 3  Question: 18
The minimum number of $2$input $NAND$ gates required to implement a $2$input $XOR$ gate is $4$ $5$ $6$ $7$
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Mar 28, 2018
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Digital Circuits
by
Milicevic3306
(
15.8k
points)

35
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gate2016ec3
digitalcircuits
combinationalcircuits
logicgates
+1
vote
0
answers
21
GATE ECE 2016 Set 3  Question: 43
Following is the Kmap of a Boolean function of five variables $P,Q,R,S$ and $X$ ... $\overline{Q}\:S\:X+\;Q\:\overline{S}\:\overline{X}$ $\overline{Q}\:S+\;Q\overline{S}$
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Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
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23
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gate2016ec3
digitalcircuits
kmap
minsumofproductsform
0
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0
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22
GATE ECE 2016 Set 3  Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
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Mar 28, 2018
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Digital Circuits
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Milicevic3306
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15.8k
points)

39
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gate2016ec3
numericalanswers
digitalcircuits
combinationalcircuits
logicgates
0
votes
0
answers
23
GATE ECE 2016 Set 3  Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}5\:\text{counter}$ $\text{mod}6\:\text{counter}$ $\text{mod}7\:\text{counter}$ $\text{mod}8\:\text{counter}$
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Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

41
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gate2016ec3
digitalcircuits
sequentialcircuit
counters
0
votes
0
answers
24
GATE ECE 2016 Set 2  Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flipflops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

35
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gate2016ec2
numericalanswers
digitalcircuits
sequentialcircuit
counters
0
votes
0
answers
25
GATE ECE 2016 Set 2  Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
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Mar 28, 2018
in
Digital Circuits
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Milicevic3306
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15.8k
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44
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gate2016ec2
digitalcircuits
combinationalcircuits
multiplexers
0
votes
0
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26
GATE ECE 2016 Set 2  Question: 42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$
asked
Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
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25
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gate2016ec2
digitalcircuits
microprocessor
rom
0
votes
0
answers
27
GATE ECE 2016 Set 2  Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second
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Mar 28, 2018
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Digital Circuits
by
Milicevic3306
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15.8k
points)

41
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gate2016ec2
digitalcircuits
analogtodigitalconverter
0
votes
0
answers
28
GATE ECE 2016 Set 2  Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.
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Mar 28, 2018
in
Digital Circuits
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Milicevic3306
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15.8k
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89
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gate2016ec2
digitalcircuits
statetransitiondiagram
0
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0
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29
GATE ECE 2016 Set 1  Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$type semiconductor.
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Mar 28, 2018
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Digital Circuits
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Milicevic3306
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15.8k
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42
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gate2016ec1
digitalcircuits
semiconductor
0
votes
0
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30
GATE ECE 2016 Set 1  Question: 12
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): As channel length reduces,OFFstate current increases. As channel length reduces,output resistance increases. As channel length reduces,threshold voltage remains constant. As channel ... . Which of the above statements are INCORRECT? P and Q P and S Q and R R and S
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Mar 28, 2018
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Digital Circuits
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Milicevic3306
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15.8k
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30
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gate2016ec1
digitalcircuits
semiconductor
mosfet
0
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0
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31
GATE ECE 2016 Set 1  Question: 43
The functionality implemented by the circuit below is $2$to$1$ multiplexer $4$to$1$ multiplexer $7$to$1$ multiplexer $6$to$1$ multiplexer
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Mar 28, 2018
in
Digital Circuits
by
Milicevic3306
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15.8k
points)

47
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gate2016ec1
digitalcircuits
combinationalcircuits
multiplexers
0
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0
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32
GATE ECE 2016 Set 1  Question: 44
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this? For POP, the data transceivers remain in the same direction as for instruction fetch ... in the stack pointer. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
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Mar 28, 2018
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Digital Circuits
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15.8k
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21
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gate2016ec1
digitalcircuits
microprocessor8085
0
votes
0
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33
GATE ECE 2015 Set 3  Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$input OR gate $3$input NOR gate $3$input AND gate $3$input XOR gate
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Mar 28, 2018
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Digital Circuits
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33
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gate2015ec3
digitalcircuits
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34
GATE ECE 2015 Set 3  Question: 16
Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$bit numbers stored in registers $B$ and $C?$ ...
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Mar 28, 2018
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Digital Circuits
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gate2015ec3
digitalcircuits
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35
GATE ECE 2015 Set 3  Question: 37
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate
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Digital Circuits
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gate2015ec3
digitalcircuits
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logicgates
0
votes
0
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36
GATE ECE 2015 Set 3  Question: 38
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the pushbutton switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing NOR gates to NAND gates inverters to buffers NOR gates to NAND gates and inverters to buffers $5\: V$ to ground
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Mar 28, 2018
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Digital Circuits
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gate2015ec3
digitalcircuits
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flipflops
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37
GATE ECE 2015 Set 3  Question: 49
Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit step sequence. Assume ݊$x_{2}[n]= \begin{cases} \sqrt{1.5}& \text{for } n = 0,1 \\ 0 &\text{otherwise.} \end{cases}$ Then the value of $\alpha$ is _________.
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Digital Circuits
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gate2015ec3
numericalanswers
digitalcircuits
0
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0
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38
GATE ECE 2015 Set 2  Question: 14
In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively, NOR, OR OR, NAND NAND, OR AND,NAND
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Mar 28, 2018
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Digital Circuits
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gate2015ec2
digitalcircuits
combinationalcircuits
logicgates
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39
GATE ECE 2015 Set 2  Question: 15
In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator? MOV B, M PCHL RNZ SBI BEH
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Mar 28, 2018
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40
GATE ECE 2015 Set 2  Question: 16
A mod$n$ counter using a synchronous binary upcounter with synchronous clear input is shown in the figure. The value of $n$ is _______.
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Digital Circuits
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gate2015ec2
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