Recent questions and answers in Digital Circuits

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1

GATE ECE 2010 | Question: 11
Match the logic gates in Column A with their equivalents in Column B. $\text{P-2, Q-4, R-1, S-3}$ $\text{P-4, Q-2, R-1, S-3}$ $\text{P-2, Q-4, R-3, S-1}$ $\text{P-4, Q-2, R-3, S-1}$

admin asked in Combinational Circuits Sep 15, 2022

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GATE ECE 2010 | Question: 12
For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be $\mathrm{A}=1, \mathrm{~B}=1, \mathrm{C}=0$ $\text{A = 1, B = 0, C = 0}$ $\mathrm{A}=0, \mathrm{~B}=1, \mathrm{C}=0$ $\text{A = 0, B = 0, C = 1}$

admin asked in Combinational Circuits Sep 15, 2022

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GATE ECE 2010 | Question: 37
Assuming that all flip-flops are in reset condition initially, the count sequence observed at $\text{Q}_\text{A}$ in the circuit shown is $0010111 \ldots$ $0001011 \ldots$ $0101111 \ldots$ $0110100 \ldots$

admin asked in Sequential Circuits Sep 15, 2022

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GATE ECE 2010 | Question: 39
The Boolean function realized by the logic circuit shown is $\text{F} = \sum_{\text{m}} (0, 1, 3, 5, 9, 10, 14)$ $\text{F}=\sum_{\text{m}}(2,3,5,7,8,12,13)$ $\text{F}=\sum_{\text{m}}(1,2,4,5,11, 14,15)$ $\text{F}= \sum_{\text{m}}(2,3,5,7,8,9,12)$

admin asked in Number Representations Sep 15, 2022

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GATE ECE 2011 | Question: 7
The logic function implemented by the circuit below is (ground implies a logic $\text{“0”})$ $\text{F=AND(P,Q})$ $\text{F=OR(P,Q})$ $\text{F=XNOR(P,Q})$ $\text{F=XOR(P,Q})$

admin asked in Number Representations Sep 3, 2022

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GATE ECE 2011 | Question: 19
The output $\mathrm{Y}$ in the circuit below is always $\text{“1"}$ when two or more of the inputs $\mathrm{P, Q, R}$ are $\text{“0"}$ two or more of the inputs $\mathrm{P, Q, R}$ are $\text{“1"}$ any odd number of the inputs $\mathrm{P, Q, R}$ is $\text{“0"}$ any odd number of the inputs $\mathrm{P, Q, R}$ is $\text{“1"}$

admin asked in Number Representations Sep 3, 2022

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7

GATE ECE 2011 | Question: 41
Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarrow 11 \rightarrow 01 \rightarrow 10 \rightarrow 00 \rightarrow \cdots$ The connections to the ...

admin asked in Sequential Circuits Sep 3, 2022

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8

GATE ECE 2021 | Question: 11
If $(1235)_{x}\:=\:(3033)_{y}$, where $x$ and $y$ indicate the bases of the corresponding numbers, then $x\:=\:7$ and $y\:=\:5$ $x\:=\:8$ and $y\:=\:6$ $x\:=\:6$ and $y\:=\:4$ $x\:=\:9$ and $y\:=\:7$

Arjun asked in Digital Circuits Feb 20, 2021

by Arjun

6.0k points

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9

GATE ECE 2021 | Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$

Arjun asked in Digital Circuits Feb 20, 2021

by Arjun

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10

GATE ECE 2021 | Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$

Arjun asked in Digital Circuits Feb 20, 2021

by Arjun

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11

GATE ECE 2021 | Question: 46
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is

Arjun asked in Digital Circuits Feb 20, 2021

by Arjun

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2 answers

12

GATE ECE 2014 Set 1 | Question: 15
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to $X$ $Y$ $XY$ $X+Y$

Hira Thakur answered in Digital Circuits Jan 5, 2021

by Hira Thakur

240 points

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1 answer

13

GATE ECE 2018 | Question: 31
A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$

Hira Thakur answered in Number Representations Jan 5, 2021

by Hira Thakur

240 points

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14

GATE ECE 2020 | Question: 10
The figure below shows a multiplexer where $S_{1}$ and $S{2}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$

Hira Thakur answered in Digital Circuits Jan 5, 2021

by Hira Thakur

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15

GATE ECE 2014 Set 1 | Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$

srestha answered in Number Representations May 19, 2020

by srestha

460 points

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16

GATE ECE 2020 | Question: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from mid-bandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$

go_editor asked in Digital Circuits Feb 13, 2020

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17

GATE ECE 2020 | Question: 19
In an $8085$ microprocessor, the number of address lines required to access a $16$ K byte memory bank is ____________ .

go_editor asked in Digital Circuits Feb 13, 2020

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18

GATE ECE 2020 | Question: 20
A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.

go_editor asked in Digital Circuits Feb 13, 2020

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19

GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$

go_editor asked in Number Representations Feb 13, 2020

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20

GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.

go_editor asked in Number Representations Feb 13, 2020

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21

GATE ECE 2019 | Question: 14
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively? $\text{0 and D}$ $\text{Hi-Z and D}$ $\text{0 and 1}$ $\text{Hi-Z and}$ $ \overline{D}$

Arjun asked in Digital Circuits Feb 12, 2019

by Arjun

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22

GATE ECE 2019 | Question: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR

Arjun asked in Digital Circuits Feb 12, 2019

by Arjun

6.0k points

126 views

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2 answers

23

GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________

Amit puri answered in Number Representations Aug 29, 2018

by Amit puri

140 points

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24

GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.

Milicevic3306 asked in Number Representations Mar 28, 2018

by Milicevic3306

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25

GATE ECE 2016 Set 3 | Question: 16
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be $4E$ and $0$ $4E$ and $1$ $4F$ and $0$ $4F$ and $1$

Milicevic3306 asked in Digital Circuits Mar 28, 2018

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26

GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$

Milicevic3306 asked in Number Representations Mar 28, 2018

by Milicevic3306

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27

GATE ECE 2016 Set 3 | Question: 18
The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is $4$ $5$ $6$ $7$

Milicevic3306 asked in Digital Circuits Mar 28, 2018

by Milicevic3306

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28

GATE ECE 2016 Set 3 | Question: 43
Following is the K-map of a Boolean function of five variables $P,Q,R,S$ and $X$ ... $\overline{Q}\:S\:X+\;Q\:\overline{S}\:\overline{X}$ $\overline{Q}\:S+\;Q\overline{S}$

Milicevic3306 asked in Digital Circuits Mar 28, 2018

by Milicevic3306

15.8k points

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29

GATE ECE 2016 Set 3 | Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________

Milicevic3306 asked in Number Representations Mar 28, 2018

by Milicevic3306

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30

GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$

Milicevic3306 asked in Number Representations Mar 28, 2018

by Milicevic3306

15.8k points

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31

GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________

Milicevic3306 asked in Number Representations Mar 28, 2018

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32

GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$

Milicevic3306 asked in Number Representations Mar 28, 2018

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33

GATE ECE 2016 Set 2 | Question: 42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$

Milicevic3306 asked in Digital Circuits Mar 28, 2018

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34

GATE ECE 2016 Set 2 | Question: 43
In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ ... maximum sampling rate? $1$ megasamples per second $6$ megasamples per second $64$ megasamples per second $256$ megasamples per second

Milicevic3306 asked in Number Representations Mar 28, 2018

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35

GATE ECE 2016 Set 2 | Question: 44
The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct? Transitions from State ... State $B$ are ambiguously defined. Transitions from State $C$ are ambiguously defined. All of the state transitions are defined unambiguously.

Milicevic3306 asked in Digital Circuits Mar 28, 2018

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36

GATE ECE 2016 Set 1 | Question: 11
A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure? Intrinsic semiconductor doped with pentavalent ... atoms to form $p$-type semiconductor. Intrinsic semiconductor doped with trivalent atoms to form $p$-type semiconductor.

Milicevic3306 asked in Number Representations Mar 28, 2018

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37

GATE ECE 2016 Set 1 | Question: 12
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): As channel length reduces,OFF-state current increases. As channel length reduces,output resistance increases. As channel length reduces,threshold voltage remains constant. As channel ... . Which of the above statements are INCORRECT? P and Q P and S Q and R R and S

Milicevic3306 asked in Digital Circuits Mar 28, 2018

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38

GATE ECE 2016 Set 1 | Question: 43
The functionality implemented by the circuit below is $2$-to-$1$ multiplexer $4$-to-$1$ multiplexer $7$-to-$1$ multiplexer $6$-to-$1$ multiplexer

Milicevic3306 asked in Digital Circuits Mar 28, 2018

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39

GATE ECE 2016 Set 1 | Question: 44
In an $8085$ system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this? For POP, the data transceivers remain in the same direction as for instruction fetch ... in the stack pointer. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.

Milicevic3306 asked in Digital Circuits Mar 28, 2018

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40

GATE ECE 2015 Set 3 | Question: 15
In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent? $3$-input OR gate $3$-input NOR gate $3$-input AND gate $3$-input XOR gate

Milicevic3306 asked in Number Representations Mar 28, 2018

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