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Recent questions and answers in Digital Circuits
2
votes
1
answer
1
GATE ECE 2010 | Question: 37
Assuming that all flip-flops are in reset condition initially, the count sequence observed at $\text{Q}_\text{A}$ in the circuit shown is $0010111 \ldots$ $0001011 \ldots$ $0101111 \ldots$ $0110100 \ldots$
minimalist
answered
in
Sequential Circuits
Dec 27, 2023
by
minimalist
910
points
246
views
gate2010-ec
digital-circuits
sequential-circuit
flip-flop
2
votes
1
answer
2
GATE ECE 2015 Set 3 | Question: 37
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE? Gate $1$ is a universal gate Gate $2$ is a universal gate Gate $3$ is a universal gate None of the gates shown is a universal gate
Deepak Poonia
answered
in
Number Representations
Oct 30, 2023
by
Deepak Poonia
1.3k
points
481
views
gate2015-ec-3
digital-circuits
combinational-circuits
logic-gates
functional-completeness
1
vote
1
answer
3
GATE ECE 2014 Set 4 | Question: 40
An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by $Y = A \: \overline{B} \:C+A \: \overline{C} \:D$ $Y = \overline{A} \: B \:C +A \: \overline{B} \: D$ $Y = A \: B \: \overline{C} + \overline{A} \: C \:D$ $Y= \overline{A} \: \overline{B} \: D + A \: \overline{B} \: C$
Deepak Poonia
answered
in
Number Representations
Oct 23, 2023
by
Deepak Poonia
1.3k
points
429
views
gate2014-ec-4
digital-circuits
combinational-circuits
multiplexers
2
votes
1
answer
4
GATE ECE 2011 | Question: 7
The logic function implemented by the circuit below is (ground implies a logic $\text{“0”})$ $\text{F=AND(P,Q})$ $\text{F=OR(P,Q})$ $\text{F=XNOR(P,Q})$ $\text{F=XOR(P,Q})$
Deepak Poonia
answered
in
Number Representations
Oct 23, 2023
by
Deepak Poonia
1.3k
points
520
views
gate2011-ec
digital-circuits
multiplexers
3
votes
1
answer
5
GATE ECE 2014 Set 1 | Question: 41
Consider the Boolean function $F(w,x,y,z) = wy + xy + \overline{w}\:xyz + \overline{w}\:\overline{x}\:y + xz + \overline{x}\:\overline{y}\:\overline{z}.$ Which one of the following is the complete set of essential prime implicants? $w,y,xz,\overline{x}\:\overline{z}$ $w,y,xz$ $y, \overline{x}\:\overline{y}\:\overline{z}$ $y,xz,\overline{x}\:\overline{z}$
minimalist
answered
in
Digital Circuits
Oct 21, 2023
by
minimalist
910
points
446
views
gate2014-ec-1
boolean-algebra
digital-circuits
3
votes
2
answers
6
GATE ECE 2011 | Question: 19
The output $\mathrm{Y}$ in the circuit below is always $\text{“1"}$ when two or more of the inputs $\mathrm{P, Q, R}$ are $\text{“0"}$ two or more of the inputs $\mathrm{P, Q, R}$ are $\text{“1"}$ any odd number of the inputs $\mathrm{P, Q, R}$ is $\text{“0"}$ any odd number of the inputs $\mathrm{P, Q, R}$ is $\text{“1"}$
minimalist
answered
in
Number Representations
Oct 21, 2023
by
minimalist
910
points
487
views
gate2011-ec
digital-circuits
combinational-circuits
logic-gates
1
vote
1
answer
7
GATE ECE 2020 | Question: 50
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{\text{setup}}$ is the setup-time, and $t_{\text{hold}}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is _________$\text{MHz}$.
Deepak Poonia
answered
in
Number Representations
Oct 17, 2023
by
Deepak Poonia
1.3k
points
901
views
gate2020-ec
numerical-answers
digital-circuits
sequential-circuit
flip-flops
2
votes
1
answer
8
GATE ECE 2010 | Question: 39
The Boolean function realized by the logic circuit shown is $\text{F} = \sum_{\text{m}} (0, 1, 3, 5, 9, 10, 14)$ $\text{F}=\sum_{\text{m}}(2,3,5,7,8,12,13)$ $\text{F}=\sum_{\text{m}}(1,2,4,5,11, 14,15)$ $\text{F}= \sum_{\text{m}}(2,3,5,7,8,9,12)$
Deepak Poonia
answered
in
Number Representations
Oct 12, 2023
by
Deepak Poonia
1.3k
points
310
views
gate2010-ec
digital-circuits
combinational-circuits
multiplexers
1
vote
1
answer
9
GATE ECE 2015 Set 1 | Question: 38
A $3$-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(a,b,\overline{c}),c)$? $3$-input NAND gate $3$-input XOR gate $3$-input NOR gate $3$-input XNOR gate
Deepak Poonia
answered
in
Digital Circuits
Oct 11, 2023
by
Deepak Poonia
1.3k
points
393
views
gate2015-ec-1
digital-circuits
logic-gates
2
votes
1
answer
10
GATE ECE 2010 | Question: 12
For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be $\mathrm{A}=1, \mathrm{~B}=1, \mathrm{C}=0$ $\text{A = 1, B = 0, C = 0}$ $\mathrm{A}=0, \mathrm{~B}=1, \mathrm{C}=0$ $\text{A = 0, B = 0, C = 1}$
Deepak Poonia
answered
in
Combinational Circuits
Oct 11, 2023
by
Deepak Poonia
1.3k
points
397
views
gate2010-ec
digital-circuits
combinational-circuits
logic-gates
2
votes
1
answer
11
GATE ECE 2016 Set 3 | Question: 43
Following is the K-map of a Boolean function of five variables $P,Q,R,S$ and $X$ ... $\overline{Q}\:S\:X+\;Q\:\overline{S}\:\overline{X}$ $\overline{Q}\:S+\;Q\overline{S}$
Deepak Poonia
answered
in
Digital Circuits
Oct 8, 2023
by
Deepak Poonia
1.3k
points
361
views
gate2016-ec-3
digital-circuits
k-map
min-sum-of-products-form
2
votes
1
answer
12
GATE ECE 2018 | Question: 9
A function $F(A, B, C)$ defined by three Boolean variables $\text{A, B and C}$ when expressed as sum of products is given by $F=\overline{A}\:.\overline{B}\:.\overline{C}+\overline{A}\:.B\:.\overline{C}+A\:.\overline{B}\:.\overline{C}$ ...
Deepak Poonia
answered
in
Digital Circuits
Oct 8, 2023
by
Deepak Poonia
1.3k
points
438
views
gate2018-ec
digital-circuits
boolean-algebra
1
vote
1
answer
13
GATE ECE 2014 Set 2 | Question: 15
The number of bytes required to represent the decimal number $1856357$ in packed BCD (Binary Coded Decimal) form is ___________.
Deepak Poonia
answered
in
Digital Circuits
Oct 8, 2023
by
Deepak Poonia
1.3k
points
562
views
gate2014-ec-2
digital-circuits
number-system
number-representation
0
votes
1
answer
14
GATE ECE 2014 Set 2 | Question: 14
For an $n$-variable Boolean function, the maximum number of prime implicants is $2(n-1)$ $n/2$ $2^{n}$ $2^{n-1}$
Deepak Poonia
answered
in
Digital Circuits
Oct 7, 2023
by
Deepak Poonia
1.3k
points
608
views
gate2014-ec-2
boolean-algebra
digital-circuits
2
votes
1
answer
15
GATE ECE 2010 | Question: 11
Match the logic gates in Column A with their equivalents in Column B. $\text{P-2, Q-4, R-1, S-3}$ $\text{P-4, Q-2, R-1, S-3}$ $\text{P-2, Q-4, R-3, S-1}$ $\text{P-4, Q-2, R-3, S-1}$
Deepak Poonia
answered
in
Combinational Circuits
Oct 7, 2023
by
Deepak Poonia
1.3k
points
550
views
gate2010-ec
digital-circuits
combinational-circuits
logic-gates
3
votes
1
answer
16
GATE ECE 2021 | Question: 11
If $(1235)_{x}\:=\:(3033)_{y}$, where $x$ and $y$ indicate the bases of the corresponding numbers, then $x\:=\:7$ and $y\:=\:5$ $x\:=\:8$ and $y\:=\:6$ $x\:=\:6$ and $y\:=\:4$ $x\:=\:9$ and $y\:=\:7$
Deepak Poonia
answered
in
Digital Circuits
Oct 7, 2023
by
Deepak Poonia
1.3k
points
690
views
gateec-2021
digital-circuits
number-system
number-representation
1
vote
0
answers
17
GATE ECE 2011 | Question: 41
Two $\text{D}$ flip-flops are connected as a synchronous counter that goes through the following $\mathrm{Q}_{\text{B}} \;\mathrm{Q}_{\mathrm{A}}$ sequence $00 \rightarrow 11 \rightarrow 01 \rightarrow 10 \rightarrow 00 \rightarrow \cdots$ The connections to the ...
admin
asked
in
Sequential Circuits
Sep 3, 2022
by
admin
46.4k
points
32
views
gate2011-ec
digital-circuits
sequential-circuit
flip-flop
0
votes
0
answers
18
GATE ECE 2021 | Question: 12
Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is $2^{8}$ $2^{32}$ $2^{15}$ $2^{19}$
Arjun
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Digital Circuits
Feb 20, 2021
by
Arjun
6.5k
points
175
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gateec-2021
digital-circuits
combinational-circuits
decoders
0
votes
0
answers
19
GATE ECE 2021 | Question: 31
The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is $3\:ns$ $5\:ns$ $6\:ns$ $7\:ns$
Arjun
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in
Digital Circuits
Feb 20, 2021
by
Arjun
6.5k
points
615
views
gateec-2021
digital-circuits
combinational-circuits
multiplexers
0
votes
0
answers
20
GATE ECE 2021 | Question: 46
The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
Arjun
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Digital Circuits
Feb 20, 2021
by
Arjun
6.5k
points
344
views
gateec-2021
numerical-answers
digital-circuits
sequential-circuit
counters
1
vote
2
answers
21
GATE ECE 2014 Set 1 | Question: 15
The Boolean expression $(X+Y)(X+\overline{Y}) + \overline{(X\;\overline{Y}) + \overline{X}}$ simplifies to $X$ $Y$ $XY$ $X+Y$
Hira Thakur
answered
in
Digital Circuits
Jan 5, 2021
by
Hira Thakur
240
points
220
views
gate2014-ec-1
digital-circuits
boolean-algebra
2
votes
1
answer
22
GATE ECE 2018 | Question: 31
A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is $\left ( UV+\overline{U}\:\overline{V}\right )\overline{W}$ ... $\left ( U\:\overline{V}+\overline{U}\:V\right )\left (\overline{W}\: \overline{X}+\overline{W}\:X\right )$
Hira Thakur
answered
in
Number Representations
Jan 5, 2021
by
Hira Thakur
240
points
431
views
gate2018-ec
digital-circuits
combinational-circuits
multiplexers
2
votes
1
answer
23
GATE ECE 2020 | Question: 10
The figure below shows a multiplexer where $S_{1}$ and $S_{0}$ are the select lines, $I_{0}$ to $I_{3}$ are the input data lines, $\text{EN}$ is the enable line, and $\text{F(P, Q, R)}$ is the output. $\text{F}$ is $PQ+\overline{Q}R.$ $PQ+Q\overline{R}.$ $P\overline{Q}R+\overline{P}Q.$ $\overline{Q}+PR.$
Hira Thakur
answered
in
Number Representations
Jan 5, 2021
by
Hira Thakur
240
points
610
views
gate2020-ec
digital-circuits
combinational-circuits
multiplexers
0
votes
1
answer
24
GATE ECE 2014 Set 1 | Question: 42
The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? Input $A$ is ... $A$ is connected to $\overline{Q1}$ and $S$ is complemented Input $A$ is connected to $\overline{Q1}$
srestha
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in
Number Representations
May 19, 2020
by
srestha
460
points
370
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gate2014-ec-1
digital-circuits
sequential-circuit
0
votes
0
answers
25
GATE ECE 2020 | Question: 6
A single crystal intrinsic semiconductor is at a temperature of $300$ $\text{K}$ with effective density of states for holes twice that of electrons. The thermal voltage is $26$ mV. The intrinsic Fermi level is shifted from mid-bandgap energy level by $18.02 \: meV$ $9.01 \: meV$ $13.45 \: meV$ $26.90 \: meV$
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Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
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199
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gate2020-ec
digital-circuits
semiconductor
0
votes
0
answers
26
GATE ECE 2020 | Question: 19
In an $8085$ microprocessor, the number of address lines required to access a $16$ K byte memory bank is ____________ .
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in
Digital Circuits
Feb 13, 2020
by
go_editor
1.9k
points
133
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gate2020-ec
numerical-answers
digital-circuits
microprocessor-8085
0
votes
0
answers
27
GATE ECE 2020 | Question: 20
A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.
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Feb 13, 2020
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go_editor
1.9k
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171
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gate2020-ec
numerical-answers
digital-circuits
data-converters
0
votes
0
answers
28
GATE ECE 2020 | Question: 32
The band diagram of a $p$-type semiconductor with a band-gap of $1$ eV is shown. Using this semiconductor, a $\text{MOS}$ capacitor having $V_{TH}$ of $-0.16 V$, ${C}'_{ox}$ of $100\:nF/cm^{2}$ and a metal work function of $3.87 \: eV$ is fabricated. There is no charge ... $1.70\times 10^{-8}$ $0.52\times 10^{-8}$ $1.41\times 10^{-8}$ $0.93\times 10^{-8}$
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171
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gate2020-ec
digital-circuits
semiconductor
0
votes
0
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29
GATE ECE 2019 | Question: 14
In the circuit shown, what are the values of $F$ for $EN=0$ and $EN=1,$ respectively? $\text{0 and D}$ $\text{Hi-Z and D}$ $\text{0 and 1}$ $\text{Hi-Z and}$ $ \overline{D}$
Arjun
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Digital Circuits
Feb 12, 2019
by
Arjun
6.5k
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161
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gate2019-ec
digital-circuits
logic-gates
0
votes
0
answers
30
GATE ECE 2019 | Question: 15
In the circuit shown, $A$ and $B$ are the inputs and $F$ is the output. What is the functionality of the circuit? Latch XNOR SRAM Cell XOR
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Feb 12, 2019
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Arjun
6.5k
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171
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gate2019-ec
digital-circuits
logic-gates
1
vote
2
answers
31
GATE ECE 2017 Set 2 | Question: 44
Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________
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Number Representations
Aug 29, 2018
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Amit puri
140
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3.3k
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gate2017-ec-2
numerical-answers
digital-circuits
combinational-circuits
adder
0
votes
0
answers
32
GATE ECE 2016 Set 3 | Question: 10
The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ ... $E_{gX}=E_{gY}=E_{gZ}$ $E_{gX}<E_{gY}<E_{gZ}$ no relationship among these band gaps exists.
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gate2016-ec-3
digital-circuits
semiconductor
0
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0
answers
33
GATE ECE 2016 Set 3 | Question: 16
In an $8085$ microprocessor, the contents of the accumulator and the carry flag are $A7$ (in hex) and $0$, respectively. If the instruction $RLC$ is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be $4E$ and $0$ $4E$ and $1$ $4F$ and $0$ $4F$ and $1$
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gate2016-ec-3
digital-circuits
microprocessor-8085
0
votes
0
answers
34
GATE ECE 2016 Set 3 | Question: 17
The logic functionality realized by the circuit shown below is $OR$ $XOR$ $NAND$ $AND$
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Number Representations
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Milicevic3306
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166
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gate2016-ec-3
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
35
GATE ECE 2016 Set 3 | Question: 18
The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is $4$ $5$ $6$ $7$
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gate2016-ec-3
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logic-gates
0
votes
0
answers
36
GATE ECE 2016 Set 3 | Question: 44
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________
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214
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gate2016-ec-3
numerical-answers
digital-circuits
combinational-circuits
logic-gates
0
votes
0
answers
37
GATE ECE 2016 Set 3 | Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}-5\:\text{counter}$ $\text{mod}-6\:\text{counter}$ $\text{mod}-7\:\text{counter}$ $\text{mod}-8\:\text{counter}$
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204
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gate2016-ec-3
digital-circuits
sequential-circuit
counters
0
votes
0
answers
38
GATE ECE 2016 Set 2 | Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
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315
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gate2016-ec-2
numerical-answers
digital-circuits
sequential-circuit
counters
0
votes
0
answers
39
GATE ECE 2016 Set 2 | Question: 18
A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select ... $I_{3}=C_{in}$ $I_{0}=0, I_{1}=C_{in},I_{2}=1$ and $I_{3}=C_{in}$
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gate2016-ec-2
digital-circuits
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0
votes
0
answers
40
GATE ECE 2016 Set 2 | Question: 42
An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, ... $\overline{A_{15}}+ \overline{A_{14}}+A_{13} \cdot A_{12}$
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digital-circuits
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