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Recent questions and answers in Digital Circuits
+1
vote
2
answers
1
GATE2017 EC2: 44
Figure Ⅰ shows a 4bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a fulladder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs ... $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at t (in ns) = ___________
answered
Aug 29, 2018
in
Digital Circuits
by
Amit puri
(
140
points)
gate2017ec2
0
votes
0
answers
2
GATE2017 EC2: 43
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the leftmost bit, then the number of times 'Out' will be 1 is ____________
asked
Nov 25, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec2
fsm
0
votes
0
answers
3
GATE2017 EC2: 45
A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is $\bar{P}\bar{Q}R+\bar{P}QR+P\bar{Q}\bar{R}$ $(\bar{P}+\bar{Q}+R)(\bar{P}+Q+R)(P+\bar{Q}+\bar{R})$ $\bar{P}\bar{Q}R+\bar{P}QR+P\bar{Q}R$ $(\bar{P}+\bar{Q}+R)(\bar{P}+Q+R)(P+\bar{Q}+R)$
asked
Nov 25, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec2
pla
0
votes
0
answers
4
GATE2017 EC2: 15
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is XNOR XOR NOR OR
asked
Nov 23, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec2
logicgates
0
votes
0
answers
5
GATE2017 EC2: 16
Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is $ \bar{X}\bar{Y}\bar{Z} + X Y +\bar{Y} Z $ $ \bar{X} Y\bar{Z} + X Z + \bar{Y} Z $ $ \bar{X} Y\bar{Z} +XY + \bar{Y} Z $ $ \bar{X}\bar{Y}\bar{Z} + XZ+ \bar{Y}Z $
asked
Nov 23, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec2
multiplexer
0
votes
0
answers
6
GATE2017 EC2: 17
In a DRAM, periodic refreshing is not required information is stored in a capacitor information is stored in a latch both read and write operations can be performed simultaneously
asked
Nov 23, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec2
semiconductormemories
0
votes
0
answers
7
GATE2017 EC1: 44
A 4bit shift register circuit configuration for rightshift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$, is shown. If the present state of the shift register is $ABCD=1101$, the number of clock cycles required to reach the state $ABCD=1111$ is _________.
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
shiftregisters
0
votes
0
answers
8
GATE2017 EC1: 43
Which one of the following gives the simplified sum of products expression for the Boolean function $F=m_{0}+m_{2}+m_{3}+m_{5}$, where $m_{0},m_{2},m_{3}$ and $m_{5}$ are minterms corresponding to the inputs $A,B$ and $C$ with $A$ as the $MSB$ and $C$ as the $LSB$? $A'B+A'BC'+AB'C$ $A'C'+A'B+AB'C$ $A'C'+AB'+AB'C$ $A'BC+A'C'+AB'C$
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
0
votes
0
answers
9
GATE2017 EC1: 45
The following FIVE instructions were executed on an 8085 microprocessor. MVI A,33H MVI B, 78H ADD B CMA ANI 32H The Accumulator value immediately after the execution of the fifth instruction is 00H 10H 11H 32H
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
0
votes
0
answers
10
GATE2017 EC1: 46
A finite state machine (FSM) is implemented using the D flipflop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic level throughout ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
digitalcommunication
0
votes
0
answers
11
GATE2017 EC1: 17
Consider the DLatch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a 50% duty cycle and $CLK2$ is a onefifth period delayed version of $CLK1$.The duty cycle at the output of the latch in percentage is _________.
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
latch
0
votes
0
answers
12
GATE2017 EC1: 15
In the latch circuit shown, the $NAND$ gates have nonzero, but unequal propagation delays. The present input condition is $P=Q=’0’$. If the input condition is changed simultaneously to $P=Q=’1’$, the outputs $X$ and $Y$ are,
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
latch
0
votes
0
answers
13
GATE2017 EC1: 16
The clock frequency of an 8085 microprocessor is 5 MHz . If the time required to execute an instruction is 1.4µs, then the number of Tstates needed for executing the instruction is 1 6 7 8
asked
Nov 17, 2017
in
Digital Circuits
by
admin
(
2.7k
points)
gate2017ec1
microprocessor
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