For Digital Circuits, we always assume that 0 and 1 are available as gate inputs. Explained HERE.
So, to check if Gate 3 is functionally complete Or not, we need to check $\{ F_3 = \overline{X} + Y, 0, 1 \}$ is functionally complete Or not.
Now apply Post’s functional completeness theorem on the set $\{ F_3 = \overline{X} + Y, 0, 1 \}.$
Do the same for Gate 1 & Gate 2. i.e. apply Post’s functional completeness theorem on the sets $\{ F_1 = X + Y, 0, 1 \}$ and $\{ F_2 = XY, 0, 1 \}.$
Functional Completeness Complete Playlist: Functional Completeness - Complete Playlist - Post's Theorem