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201
GATE ECE 1997 | Question 2.2
A cascade amplifier stage is equivalent to a common emitter stage followed by a common base stage a common base stage followed by an emitter follower an emitter follower stage followed by a common base stage a common base stage followed by a common emitter stage
A cascade amplifier stage is equivalent toa common emitter stage followed by a common base stagea common base stage followed by an emitter followeran emitter follower sta...
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202
GATE ECE 1997 | Question 2.3
For a $\text{MOS}$ capacitor fabricated on a $p$-type semiconductor, strong inversion occurs when surface potential is equal to Fermi potential surface potential is zero surface potential is negative and equal to Fermi potential in magnitude surface potential is positive and equal to twice the Fermi potential
For a $\text{MOS}$ capacitor fabricated on a $p$-type semiconductor, strong inversion occurs whensurface potential is equal to Fermi potentialsurface potential is zerosur...
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204
GATE ECE 1997 | Question 2.5
Each cell of a Static Random Access Memory contains $6 \; \text{MOS}$ transistors $4 \; \mathrm{MOS}$ transistors and $2$ capacitors $2 \; \text{MOS}$ transistors and $4$ capacitors $1 \; \text{MOS}$ transistor and $1$ capacitor
Each cell of a Static Random Access Memory contains$6 \; \text{MOS}$ transistors$4 \; \mathrm{MOS}$ transistors and $2$ capacitors$2 \; \text{MOS}$ transistors and $4$ ca...
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205
GATE ECE 1997 | Question 2.6
A $2$ bit binary multiplier can be implemented using $2$ inputs $\text{ANDs}$ only $2$ input $\text{XOR s}$ and $4$ input $\text{AND}$ gates only Two $2$ inputs $\text{NORs}$ and one $\text{XNOR}$ gate $\text{XOR}$ gates and shift registers
A $2$ bit binary multiplier can be implemented using$2$ inputs $\text{ANDs}$ only$2$ input $\text{XOR s}$ and $4$ input $\text{AND}$ gates onlyTwo $2$ inputs $\text{NORs}...
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206
GATE ECE 1997 | Question 2.7
In standard $\text{TTL}$, the 'totem pole' stage refers to the multi-emitter input stage the phase splitter the output buffer open collector output stage
In standard $\text{TTL}$, the 'totem pole' stage refers tothe multi-emitter input stagethe phase splitterthe output bufferopen collector output stage
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208
GATE ECE 1997 | Question 2.9
The output of the logic gate in the figure is $0$ $1$ $\text{A}$ $\mathrm{F}$
The output of the logic gate in the figure is$0$$1$$\text{A}$$\mathrm{F}$
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209
GATE ECE 1997 | Question 2.10
In an $8085 \; \mu \; \mathrm{P}$ system, the $\text{RST}$ instruction will cause an interrupt only if an interrupt service routine is not being executed only if a bit in the interrupt mask is made $0$ only if interrupts have been enabled by an $\text{El}$ instruction None of the above
In an $8085 \; \mu \; \mathrm{P}$ system, the $\text{RST}$ instruction will cause an interruptonly if an interrupt service routine is not being executedonly if a bit in t...
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210
GATE ECE 1997 | Question 3.1
In the circuit of the figure is the energy absorbed by the $4 \; \Omega$ resistor in the time interval $(0, \infty)$ is $36$ Joules $16$ Joules $256$ Joules None of the above
In the circuit of the figure is the energy absorbed by the $4 \; \Omega$ resistor in the time interval $(0, \infty)$ is$36$ Joules$16$ Joules$256$ JoulesNone of the above...
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211
GATE ECE 1997 | Question 3.2
In the circuit of the figure is the equivalent impedance seen across terminals $\text{a, b}$ is $\left(\frac{16}{3}\right) \Omega$ $\left(\frac{8}{3}\right) \Omega$ $\left(\frac{8}{3}+12 j\right) \Omega$ None of the above
In the circuit of the figure is the equivalent impedance seen across terminals $\text{a, b}$ is$\left(\frac{16}{3}\right) \Omega$$\left(\frac{8}{3}\right) \Omega$$\left(\...
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212
GATE ECE 1997 | Question 3.3
In the circuit of in the figure is the current $i_{D}$ through the ideal diode (zero cut in voltage and forward resistance) equals $0 \mathrm{~A}$ $4 \mathrm{~A}$ $1 \mathrm{~A}$ None of the above
In the circuit of in the figure is the current $i_{D}$ through the ideal diode (zero cut in voltage and forward resistance) equals$0 \mathrm{~A}$$4 \mathrm{~A}$$1 \mathrm...
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213
GATE ECE 1997 | Question 3.4
In the signal flow graph of the figure is $\text{y/ x}$ equals $3$ $\frac{5}{2}$ $2$ None of the above
In the signal flow graph of the figure is $\text{y/ x}$ equals$3$$\frac{5}{2}$$2$None of the above
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215
GATE ECE 1997 | Question 3.6
A communication channel has first-order low pass transfer function. The channel is used to transmit pulses at a symbol rate greater than the half-power frequency of the low pass function. Which of the network shown in the figure is can be used to equalise the received pulses?
A communication channel has first-order low pass transfer function. The channel is used to transmit pulses at a symbol rate greater than the half-power frequency of the l...
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216
GATE ECE 1997 | Question 3.7
The power spectral density of a deterministic signal is given by $\left[\sin (f) / f^{2}\right]$ where $f$ is frequency. The autocorrelation function of this signal in the time domain is a rectangular pulse a delta function a sine pulse a triangular pulse
The power spectral density of a deterministic signal is given by $\left[\sin (f) / f^{2}\right]$ where $f$ is frequency. The autocorrelation function of this signal in th...
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218
GATE ECE 1997 | Question 3.9
A parabolic dish antenna has a conical beam $2^{\circ}$ wide, the directivity of the antenna is approximately $20 \; d \mathrm{B}$ $30 \; d \mathrm{B}$ $40 \; d \mathrm{B}$ $50 \; d \mathrm{B}$
A parabolic dish antenna has a conical beam $2^{\circ}$ wide, the directivity of the antenna is approximately$20 \; d \mathrm{B}$$30 \; d \mathrm{B}$$40 \; d \mathrm{B}$$...
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219
GATE ECE 1997 | Question 3.10
A very lossy, $\lambda / 4$ long, $50 \; \Omega$ transmission line is open circuited at the load end. The input impedance measured at the other end of the line is approximately $0$ $50 \; \Omega$ $\infty$ None of the above
A very lossy, $\lambda / 4$ long, $50 \; \Omega$ transmission line is open circuited at the load end. The input impedance measured at the other end of the line is approxi...
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221
GATE ECE 1997 | Question 4.1
The output voltage $V_{0}$ of the circuit shown in the figure is $-4 \mathrm{~V}$ $6 \mathrm{~V}$ $5 \mathrm{~V}$ $-5.5 \mathrm{~V}$
The output voltage $V_{0}$ of the circuit shown in the figure is$-4 \mathrm{~V}$$6 \mathrm{~V}$$5 \mathrm{~V}$$-5.5 \mathrm{~V}$
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223
GATE ECE 1997 | Question 4.3
The following insturctions have been executed by an $8085 \; \mu \mathrm{P}$ ... $6019$ $6379$ $6979$ None of the above
The following insturctions have been executed by an $8085 \; \mu \mathrm{P}$$\begin{array}{cl}\text { ADDRESS (HEX) } & \text { INSTRUCTION } \\ 6010 & \text { LXI H, 8A ...
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225
GATE ECE 1997 | Question 4.5
A half wave rectifier uses a diode with a forward resistance $\text{Rf}$. The voltage is $\text{V}_\text{m} \sin \omega t$ and the load resistance is $\text{R}_\text{L}$. The $\text{DC}$ ... $\frac{2 \mathrm{Vm}}{\sqrt{\pi}}$ $\frac{\mathrm{V}_{m}}{\mathrm{R}_{\mathrm{L}}}$
A half wave rectifier uses a diode with a forward resistance $\text{Rf}$. The voltage is $\text{V}_\text{m} \sin \omega t$ and the load resistance is $\text{R}_\text{L}$....
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226
GATE ECE 1997 | Question 4.6
The intrinsic carrier density at $300 \mathrm{~K}$ is $1.5 \times 10^{10}$ / $\mathrm{cm}^{3}$, in silicon. For $n$-type silicon doped to $2.25 \times$ $10^{15}$ atoms $/ \mathrm{cm}^{3}$ ... $n=1.5 \times 10^{10} / \mathrm{cm}^{3}, p=1.5 \times 10^{10} / \mathrm{cm}^{3}$
The intrinsic carrier density at $300 \mathrm{~K}$ is $1.5 \times 10^{10}$ / $\mathrm{cm}^{3}$, in silicon. For $n$-type silicon doped to $2.25 \times$ $10^{15}$ atoms $/...
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227
GATE ECE 1997 | Question 4.7
For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is $\overline{\mathrm{ABCDE}}$ $(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\mathrm{D}+\mathrm{E}})$ ... $(\overline{\mathrm{A}+\mathrm{B}}) \cdot \mathrm{C}+\overline{\mathrm{D}} \cdot \overline{\mathrm{E}}$
For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is$\overline{\mathrm{ABCDE}}$$(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\...
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228
GATE ECE 1997 | Question 4.8
In a $\text{J-K}$ flip-flip we have $\text{J=Q}$ and $\text{K}=1$. Assuming the flip flop was initially cleared and then clocked for $6$ puleses, the sequence at the $\text{Q}$ output will be $010000$ $011001$ $010010$ $010101$
In a $\text{J-K}$ flip-flip we have $\text{J=Q}$ and $\text{K}=1$. Assuming the flip flop was initially cleared and then clocked for $6$ puleses, the sequence at the $\te...
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230
GATE ECE 1997 | Question 4.10
The boolean function $\mathrm{A}+\mathrm{BC}$ is a reduced form of $\mathrm{AB}+\mathrm{BC}$ $(\mathrm{A}+\mathrm{B}) \cdot(\mathrm{A}+\mathrm{C})$ $\overline{\mathrm{A}} \mathrm{B}+\mathrm{A} \overline{\mathrm{B}} \mathrm{C}$ $(\mathrm{A}+\mathrm{C}) \cdot \mathrm{B}$
The boolean function $\mathrm{A}+\mathrm{BC}$ is a reduced form of$\mathrm{AB}+\mathrm{BC}$$(\mathrm{A}+\mathrm{B}) \cdot(\mathrm{A}+\mathrm{C})$$\overline{\mathrm{A}} \m...
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231
GATE ECE 1997 | Question 5.1
In the case of a linear time invariant system (1) Poles in the right half plane implies Exponential decay of output (2) Impulse response zero for $t \leq 0$ implies System is casual No stored energy in the system System is unstable.
In the case of a linear time invariant system(1) Poles in the right half plane implies Exponential decay of output(2) Impulse response zero for $t \leq 0$ impliesSystem i...
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232
GATE ECE 1997 | Question 5.2
If the Fourier Transform of deterministic signal $\mathrm{g}(\mathrm{t})$ is $\mathrm{G}(f)$, then (1) The Fourier Transform of $g(t-2)$ is $G(f) e^{-j(4 \pi f)}$ (2) The Fourier Transform of $g(t / 2)$ is $G(2 f)$ $2 G(2 f)$ $G(f-2)$
If the Fourier Transform of deterministic signal $\mathrm{g}(\mathrm{t})$ is $\mathrm{G}(f)$, then(1) The Fourier Transform of $g(t-2)$ is$G(f) e^{-j(4 \pi f)}$(2) The Fo...
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233
GATE ECE 1997 | Question 5.3
(1) An $8$-bit wide $5$ word sequential memory will have $8$ Fixed $\text{‘AND'}$ gates and $4$ programmable $\text{‘OR'}$ gates (2) A $256 \times 4$ $\text{EFROM}$ has Eight $4$ bit shift registers $4$ words of $32$ bits each $8$ address pins and $4$ data pins output
(1) An $8$-bit wide $5$ word sequential memory will have$8$ Fixed $\text{‘AND'}$ gates and $4$ programmable $\text{‘OR'}$ gates(2) A $256 \times 4$ $\text{EFROM}$ has...
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234
GATE ECE 1997 | Question 5.4
(1) Wave tilt Under-water propagation (2) Faraday Rotation Ground wave propagation Space wave propagation Ionospheric propagation
(1) Wave tiltUnder-water propagation(2) Faraday RotationGround wave propagationSpace wave propagationIonospheric propagation
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235
GATE ECE 1997 | Question 5.5
While moving data between registers of the $8085$ and the stack (1) a $\text{PUSH}$ instruction Pre increments the stack pointer (2) a $\text{POP}$ instruction Post increments the stack pointer Pre decrements the stack pointer Post decrements the stack pointer
While moving data between registers of the $8085$ and the stack(1) a $\text{PUSH}$ instructionPre increments the stack pointer(2) a $\text{POP}$ instructionPost increment...
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236
GATE ECE 1997 | Question 5.6
Negative feedback in (1) Voltage series configuration increase input impedance (2) Current shunt configuration decrease input impedance increases closed loop gain leads to oscillation
Negative feedback in(1) Voltage series configurationincrease input impedance(2) Current shunt configurationdecrease input impedanceincreases closed loop gainleads to osci...
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