Register

GATE ECE 1997 | Question 4.9

• recategorized by
341 views
0 0 votes

The gate delay of an $\text{NMOS}$ inverter is dominated by charge time rather than discharge time because

  1. the driver transistor has larger threshold voltage than the load transistor
  2. the driver transistor has larger leakage currents compared to the load transistor
  3. the load transistor has a smaller $\text{W/L}$ ratio compared to the driver transistor
  4. none of the above

Please log in or register to answer this question.

Answer:
← Previous · GATE ECE 1997 | Ques...Next → · GATE ECE 1997 | Ques...
← Previous in category · GATE ECE 1997 | Ques...Next in category → · GATE ECE 1997 | Ques...
Position:
Show:
Voting & Accepting an answer helps improve the community

Related questions

1 1 vote
0 0 answers
462
462 views
admin asked Oct 2, 2022
462 views
GATE ECE 1997 | Question 4.7
For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is$\overline{\mathrm{ABCDE}}$$(\mathrm{AB}+\overline{\mathrm{C}}) \cdot(\overline{\...
0 0 votes
0 0 answers
469
469 views
admin asked Oct 2, 2022
469 views
GATE ECE 1997 | Question 2.6
A $2$ bit binary multiplier can be implemented using$2$ inputs $\text{ANDs}$ only$2$ input $\text{XOR s}$ and $4$ input $\text{AND}$ gates onlyTwo $2$ inputs $\text{NORs}...
0 0 votes
0 0 answers
550
550 views
admin asked Oct 2, 2022
550 views
GATE ECE 1997 | Question 2.7
In standard $\text{TTL}$, the 'totem pole' stage refers tothe multi-emitter input stagethe phase splitterthe output bufferopen collector output stage
0 0 votes
0 0 answers
504
504 views
admin asked Oct 2, 2022
504 views
GATE ECE 1997 | Question 2.8
The inverter $74 \; \mathrm{ALSO} 4$ has the following specifications\[ \begin{array}{l}\mathrm{I}_{\text {OH } \max }=-0.4 \mathrm{~mA}, \mathrm{l}_{\text {OLmax }}=8 \m...

Add Synced Question

×