Recent questions tagged counters

The ripple counter shown in the given figure works as a$\bmod -3$ up counter$\bmod -5$ up counter$\bmod - 3$ down counter$\bmod - 5$ down counter

The figure shows a mod-$\mathrm{K}$ counter, here $\mathrm{K}$ is equal to$1$$2$$3$$4$

The $\text{mod}-5$ counter shown in the figure is counts through states $Q_{2} Q_{1} Q_{0}=000,001,010,011$ and $100$(a) Will the counter lockout if it happen to be in an...

For the circuit shown, the counter state $\left(\mathrm{Q}_{1} \mathrm{Q}_{0}\right)$ follows the sequence$00,01,10,11,00 \ldots$$00,01,10,00,01 \ldots$$00,01,11,00,01 \l...

What are the counting states $\left(Q_{1}, Q_{2}\right)$ for the counter shown in the figure below?$11,10,00,11,10, \ldots$$01,10,11,00,01, \ldots$$00,11,01,10,00, \ldots...

The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to ...

For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$...

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, ...

A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod-$2$ counter mod-$4$ counter mod-$5$ counter mod-...

A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_...