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Recent questions tagged counters
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GATE EC 2021  Question: 46
The propagation delay of the exclusive$\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flipflops is assumed to be zero. The clock ($\text{Clk}$ ... of triggering clock edges after which the flipflop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
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GATE ECE 2016 Set 3  Question: 45
For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a $\text{mod}5\:\text{counter}$ $\text{mod}6\:\text{counter}$ $\text{mod}7\:\text{counter}$ $\text{mod}8\:\text{counter}$
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Mar 28, 2018
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GATE ECE 2016 Set 2  Question: 17
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flipflops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with ... $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in $mW$) in the resistor $R$ is _________
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Mar 28, 2018
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GATE ECE 2015 Set 2  Question: 16
A mod$n$ counter using a synchronous binary upcounter with synchronous clear input is shown in the figure. The value of $n$ is _______.
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Mar 28, 2018
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GATE ECE 2015 Set 2  Question: 37
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a mod$2$ counter mod$4$ counter mod$5$ counter mod$6$ counter
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Mar 28, 2018
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GATE ECE 2017 Set 1  Question: 46
A finite state machine (FSM) is implemented using the D flipflop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are $Q_{A}Q_{B}=00,01,10$ and $11$. Assume that $X_{IN}$ is held at a constant logic ... states if $X_{IN}=0$ only two or four possible states if $X_{IN}=1$ only two or four possible states if $X_{IN}=0$
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Nov 17, 2017
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